_primary.vhd

来自「viterbi decoder , use verilog HDL langua」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity controller is
    port(
        sync_s1         : in     vl_logic;
        self_test_s1    : in     vl_logic;
        decoded_column_s1: in     vl_logic_vector(3 downto 0);
        external_y_s1   : in     vl_logic_vector(1 downto 0);
        sel_initial_s1  : out    vl_logic;
        data_valid_s1   : out    vl_logic;
        fail_s1         : out    vl_logic;
        orig_del_bit_s1 : out    vl_logic;
        decoded_bit_s1  : out    vl_logic;
        y2_s1           : out    vl_logic;
        y1_s1           : out    vl_logic;
        phi1            : in     vl_logic;
        phi2            : in     vl_logic
    );
end controller;