📄 mt48lc4m32b2.v
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end always @(negedge ras_in[1]) begin:TRASfall1 ras_out[1] <= #tdevice_TRASmax ras_in[1]; end always @(posedge ras_in[2]) begin:TRASrise2 ras_out[2] <= #tdevice_TRASmin ras_in[2]; end always @(negedge ras_in[2]) begin:TRASfall2 ras_out[2] <= #tdevice_TRASmax ras_in[2]; end always @(posedge ras_in[3]) begin:TRASrise3 ras_out[3] <= #tdevice_TRASmin ras_in[3]; end always @(negedge ras_in[3]) begin:TRASfall3 ras_out[3] <= #tdevice_TRASmax ras_in[3]; end always @(posedge rcdt_in[0]) begin:TRCDrise0 rcdt_out[0] <= #5 1'b1; end always @(negedge rcdt_in[0]) begin:TRCDfall0 rcdt_out[0] <= #tdevice_TRCD 1'b0; end always @(posedge rcdt_in[1]) begin:TRCDrise1 rcdt_out[1] <= #5 1'b1; end always @(negedge rcdt_in[1]) begin:TRCDfall1 rcdt_out[1] <= #tdevice_TRCD 1'b0; end always @(posedge rcdt_in[2]) begin:TRCDrise2 rcdt_out[2] <= #5 1'b1; end always @(negedge rcdt_in[2]) begin:TRCDfall2 rcdt_out[2] <= #tdevice_TRCD 1'b0; end always @(posedge rcdt_in[3]) begin:TRCDrise3 rcdt_out[3] <= #5 1'b1; end always @(negedge rcdt_in[3]) begin:TRCDfall3 rcdt_out[3] <= #tdevice_TRCD 1'b0; end ///////////////////////////////////////////////////////////////////////// // Functional Section ///////////////////////////////////////////////////////////////////////// always @(posedge CLK) begin if ($time > Next_Ref && PoweredUp && Ref_Cnt > 0) begin Ref_Cnt = Ref_Cnt - 1; Next_Ref = $time + tdevice_REF; end if (CKEreg) begin if (~CSNeg_ipd) chip_en = 1; else chip_en = 0; end if (CKEreg && ~CSNeg_ipd) begin if (DQM0_ipd == 1'bx) $display(" Unusable value for DQM0 "); if (DQM1_ipd == 1'bx) $display(" Unusable value for DQM1 "); if (DQM2_ipd == 1'bx) $display(" Unusable value for DQM2 "); if (DQM3_ipd == 1'bx) $display(" Unusable value for DQM3 "); if (WENeg_ipd == 1'bx) $display(" Unusable value for WENeg "); if (RASNeg_ipd == 1'bx) $display(" Unusable value for RASNeg "); if (CASNeg_ipd == 1'bx) $display(" Unusable value for CASNeg "); // Command Decode if (RASNeg_ipd && CASNeg_ipd && WENeg_ipd) command = nop; else if (~RASNeg_ipd && CASNeg_ipd && WENeg_ipd) command = act; else if (RASNeg_ipd && ~CASNeg_ipd && WENeg_ipd) command = rd; else if (RASNeg_ipd && ~CASNeg_ipd && ~WENeg_ipd) command = writ; else if (RASNeg_ipd && CASNeg_ipd && ~WENeg_ipd) command = bst; else if (~RASNeg_ipd && CASNeg_ipd && ~WENeg_ipd) command = pre; else if (~RASNeg_ipd && ~CASNeg_ipd && WENeg_ipd) command = ref; else if (~RASNeg_ipd && ~CASNeg_ipd && ~WENeg_ipd) command = mrs; // PowerUp Check if (~(PoweredUp) && command != nop) begin $display (" Incorrect power up. Command issued before "); $display (" power up complete. "); end // Bank Decode if (~BA0_ipd && ~BA1_ipd) cur_bank = 0; else if (BA0_ipd && ~BA1_ipd) cur_bank = 1; else if (~BA0_ipd && BA1_ipd) cur_bank = 2; else if (BA0_ipd && BA1_ipd) cur_bank = 3; else begin $display ("Could not decode bank selection - results"); $display ("may be incorrect."); end end // The Big State Machine if (CKEreg) begin if (CSNeg_ipd == 1'bx) $display ("Unusable value for CSNeg"); if (CSNeg_ipd) command = nop; // DQM pipeline DQM0_reg2 = DQM0_reg1; DQM0_reg1 = DQM0_reg0; DQM0_reg0 = DQM0_ipd; DQM1_reg2 = DQM1_reg1; DQM1_reg1 = DQM1_reg0; DQM1_reg0 = DQM1_ipd; DQM2_reg2 = DQM2_reg1; DQM2_reg1 = DQM2_reg0; DQM2_reg0 = DQM2_ipd; DQM3_reg2 = DQM3_reg1; DQM3_reg1 = DQM3_reg0; DQM3_reg0 = DQM3_ipd; // by default data drive is Z, might get over written in one // of the passes below DataDrive = 32'bz; for (bank = 0; bank <= hi_bank; bank = bank + 1) begin case (statebank[bank]) pwron : begin if (~DQM0_ipd) begin $display ("DQM0 must be held high during"); $display ("initialization."); end if (~DQM1_ipd) begin $display ("DQM1 must be held high during"); $display ("initialization."); end if (~DQM2_ipd) begin $display ("DQM2 must be held high during"); $display ("initialization."); end if (~DQM3_ipd) begin $display ("DQM3 must be held high during"); $display ("initialization."); end if (~PoweredUp) begin if (command != nop) $display ("Only NOPs allowed during power up."); DataDrive = 32'bz; end else if (command == pre && (cur_bank == bank || A[10])) begin statebank[bank] = precharge; statebank[bank] <= #tdevice_TRP idle; end end precharge : begin if (cur_bank == bank) // It is only an error if this bank is selected if (command != nop && command != pre) begin $display ("Illegal command received "); $display ("during precharge.",$time); end end idle : begin if (command == nop || command == bst || command == pre || cur_bank != bank) begin end else if (command == mrs) begin if (statebank[0] == idle && statebank[1] == idle && statebank[2] == idle && statebank[3] == idle) begin ModeReg = A; statebank[bank] = mode_set; end end else if (command == ref) begin if (statebank[0] == idle && statebank[1] == idle && statebank[2] == idle && statebank[3] == idle) if (CKE) begin statebank[bank] = auto_refresh; statebank[bank] <= #tdevice_TRCAR idle; end else begin statebank[0] = self_refresh; statebank[1] = self_refresh; statebank[2] = self_refresh; statebank[3] = self_refresh; end end else if (command == act) begin statebank[bank] = bank_act; ras_in[bank] = 1'b1; ras_in [bank] <= #70 1'b0; rct_in = 1'b1; rct_in <= #1 1'b0; rcdt_in[bank] = 1'b1; rcdt_in[bank] <= #1 1'b0; MemAddr[bank][19:8] = A; // latch row addr end else $display ("Illegal command received in idle state.",$time); end mode_set : begin if (ModeReg[7] != 0 || ModeReg[8] != 0) $display ("Illegal operating mode set."); if (command != nop) begin $display ("Illegal command received during mode"); $display ("set.",$time); end // read burst length if (ModeReg[2:0] == 3'b000) begin BurstLen = 1; Burst_Bits = 0; end else if (ModeReg[2:0] == 3'b001) begin BurstLen = 2; Burst_Bits = 1; end else if (ModeReg[2:0] == 3'b010) begin BurstLen = 4; Burst_Bits = 2; end else if (ModeReg[2:0] == 3'b011) begin BurstLen = 8; Burst_Bits = 3; end else if (ModeReg[2:0] == 3'b111) begin BurstLen = 256; Burst_Bits = 7; end else $display ("Invalid burst length specified."); // read burst type if (~ModeReg[3]) Burst = sequential; else if (ModeReg[3]) Burst = interleave; else $display ("Invalid burst type specified."); // read CAS latency if (ModeReg[6:4] == 3'b001) begin CAS_Lat = 1'b1; CAS_Lat2 = 1'b0; end else if (ModeReg[6:4] == 3'b010) begin CAS_Lat = 1'b0; CAS_Lat2 = 1'b1; end else if (ModeReg[6:4] == 3'b011) begin CAS_Lat = 1'b1; CAS_Lat2 = 1'b1; end else $display ("CAS Latency set incorrecty"); // write burst mode if (~ModeReg[9]) WB = programmed; else if (ModeReg[9]) WB = single; else $display ("Invalid burst type specified."); statebank[bank] = idle; end auto_refresh : begin if (Ref_Cnt < 4096) Ref_Cnt = Ref_Cnt + 1; if (command != nop) begin $display ("Illegal command received during"); $display ("auto_refresh.",$time); end end bank_act : begin if (command == pre && (cur_bank == bank || A[10])) begin if (~ras_out[bank])
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