clk_div.tan.summary

来自「自己编写的任意分频VHDL程序」· SUMMARY 代码 · 共 37 行

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.864 ns
From           : temp2
To             : clk_out
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : 222.92 MHz ( period = 4.486 ns )
From           : a2[3]
To             : a2[4]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------