clk_div.fit.summary

自己编写的任意分频VHDL程序

Fitter Status : Successful - Thu Apr 12 20:52:25 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : clk_div
Top-level Entity Name : clk_div
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
Total logic elements : 26 / 12,060 ( < 1 % )
Total pins : 2 / 173 ( 1 % )
Total virtual pins : 0
Total memory bits : 0 / 239,616 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )