📄 clk_div.tan.rpt
字号:
; N/A ; 262.95 MHz ( period = 3.803 ns ) ; a2[0] ; a2[1] ; clock ; clock ; None ; None ; 3.542 ns ;
; N/A ; 266.88 MHz ( period = 3.747 ns ) ; a2[2] ; a2[2] ; clock ; clock ; None ; None ; 3.486 ns ;
; N/A ; 266.95 MHz ( period = 3.746 ns ) ; a1[3] ; a2[4] ; clock ; clock ; None ; None ; 1.612 ns ;
; N/A ; 267.24 MHz ( period = 3.742 ns ) ; a1[3] ; a2[3] ; clock ; clock ; None ; None ; 1.610 ns ;
; N/A ; 269.11 MHz ( period = 3.716 ns ) ; a2[0] ; a2[2] ; clock ; clock ; None ; None ; 3.455 ns ;
; N/A ; 273.67 MHz ( period = 3.654 ns ) ; a1[2] ; a2[2] ; clock ; clock ; None ; None ; 1.566 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a2[2] ; a2[0] ; clock ; clock ; None ; None ; 3.301 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[1] ; a2[1] ; clock ; clock ; None ; None ; 1.491 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[2] ; a2[4] ; clock ; clock ; None ; None ; 1.435 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[0] ; a2[1] ; clock ; clock ; None ; None ; 1.275 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[0] ; a2[0] ; clock ; clock ; None ; None ; 1.273 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a2[1] ; a2[0] ; clock ; clock ; None ; None ; 2.771 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a2[4] ; a2[0] ; clock ; clock ; None ; None ; 2.751 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[0] ; a2[3] ; clock ; clock ; None ; None ; 1.184 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a2[0] ; a2[0] ; clock ; clock ; None ; None ; 2.529 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[2] ; a1[3] ; clock ; clock ; None ; None ; 2.410 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[4] ; a1[2] ; clock ; clock ; None ; None ; 2.392 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[1] ; a1[3] ; clock ; clock ; None ; None ; 2.368 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[3] ; a1[3] ; clock ; clock ; None ; None ; 2.321 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[1] ; a1[0] ; clock ; clock ; None ; None ; 2.309 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[0] ; a1[4] ; clock ; clock ; None ; None ; 2.279 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[1] ; a1[2] ; clock ; clock ; None ; None ; 2.210 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[2] ; a1[2] ; clock ; clock ; None ; None ; 2.175 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[1] ; a1[4] ; clock ; clock ; None ; None ; 2.156 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[3] ; a1[2] ; clock ; clock ; None ; None ; 2.153 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[4] ; a1[4] ; clock ; clock ; None ; None ; 2.140 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[4] ; a1[3] ; clock ; clock ; None ; None ; 2.139 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[2] ; a1[0] ; clock ; clock ; None ; None ; 2.098 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[3] ; a1[0] ; clock ; clock ; None ; None ; 2.076 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[0] ; a1[2] ; clock ; clock ; None ; None ; 2.044 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[4] ; a1[0] ; clock ; clock ; None ; None ; 1.957 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[2] ; a1[4] ; clock ; clock ; None ; None ; 1.923 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[3] ; a1[4] ; clock ; clock ; None ; None ; 1.901 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[0] ; a1[3] ; clock ; clock ; None ; None ; 1.895 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[2] ; temp1 ; clock ; clock ; None ; None ; 1.515 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a2[3] ; temp2 ; clock ; clock ; None ; None ; 1.389 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a2[4] ; temp2 ; clock ; clock ; None ; None ; 1.297 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a2[1] ; temp2 ; clock ; clock ; None ; None ; 1.279 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[0] ; a1[0] ; clock ; clock ; None ; None ; 1.159 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a2[2] ; temp2 ; clock ; clock ; None ; None ; 1.110 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[4] ; temp1 ; clock ; clock ; None ; None ; 1.106 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[1] ; temp1 ; clock ; clock ; None ; None ; 1.103 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[1] ; a1[1] ; clock ; clock ; None ; None ; 1.062 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[3] ; temp1 ; clock ; clock ; None ; None ; 1.046 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; a1[0] ; a1[1] ; clock ; clock ; None ; None ; 0.882 ns ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------+---------+------------+
; N/A ; None ; 8.864 ns ; temp2 ; clk_out ; clock ;
; N/A ; None ; 8.454 ns ; temp1 ; clk_out ; clock ;
+-------+--------------+------------+-------+---------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Apr 12 20:52:32 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clk_div -c clk_div --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 222.92 MHz between source register "a2[3]" and destination register "a2[4]" (period= 4.486 ns)
Info: + Longest register to register delay is 4.225 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X44_Y10_N4; Fanout = 6; REG Node = 'a2[3]'
Info: 2: + IC(0.782 ns) + CELL(0.442 ns) = 1.224 ns; Loc. = LC_X43_Y10_N0; Fanout = 8; COMB Node = 'LessThan3~60'
Info: 3: + IC(0.441 ns) + CELL(0.432 ns) = 2.097 ns; Loc. = LC_X43_Y10_N5; Fanout = 2; COMB Node = 'Add1~203COUT1_205'
Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 2.177 ns; Loc. = LC_X43_Y10_N6; Fanout = 2; COMB Node = 'Add1~194COUT1'
Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 2.257 ns; Loc. = LC_X43_Y10_N7; Fanout = 2; COMB Node = 'Add1~199COUT1_206'
Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 2.337 ns; Loc. = LC_X43_Y10_N8; Fanout = 1; COMB Node = 'Add1~197COUT1_207'
Info: 7: + IC(0.000 ns) + CELL(0.608 ns) = 2.945 ns; Loc. = LC_X43_Y10_N9; Fanout = 1; COMB Node = 'Add1~200'
Info: 8: + IC(0.673 ns) + CELL(0.607 ns) = 4.225 ns; Loc. = LC_X44_Y10_N2; Fanout = 4; REG Node = 'a2[4]'
Info: Total cell delay = 2.329 ns ( 55.12 % )
Info: Total interconnect delay = 1.896 ns ( 44.88 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clock" to destination register is 3.111 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 12; CLK Node = 'clock'
Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X44_Y10_N2; Fanout = 4; REG Node = 'a2[4]'
Info: Total cell delay = 2.180 ns ( 70.07 % )
Info: Total interconnect delay = 0.931 ns ( 29.93 % )
Info: - Longest clock path from clock "clock" to source register is 3.111 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 12; CLK Node = 'clock'
Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X44_Y10_N4; Fanout = 6; REG Node = 'a2[3]'
Info: Total cell delay = 2.180 ns ( 70.07 % )
Info: Total interconnect delay = 0.931 ns ( 29.93 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clock" to destination pin "clk_out" through register "temp2" is 8.864 ns
Info: + Longest clock path from clock "clock" to source register is 3.111 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 12; CLK Node = 'clock'
Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X43_Y10_N0; Fanout = 1; REG Node = 'temp2'
Info: Total cell delay = 2.180 ns ( 70.07 % )
Info: Total interconnect delay = 0.931 ns ( 29.93 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 5.529 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X43_Y10_N0; Fanout = 1; REG Node = 'temp2'
Info: 2: + IC(1.141 ns) + CELL(0.114 ns) = 1.255 ns; Loc. = LC_X45_Y10_N4; Fanout = 1; COMB Node = 'temp~0'
Info: 3: + IC(2.150 ns) + CELL(2.124 ns) = 5.529 ns; Loc. = PIN_143; Fanout = 0; PIN Node = 'clk_out'
Info: Total cell delay = 2.238 ns ( 40.48 % )
Info: Total interconnect delay = 3.291 ns ( 59.52 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Thu Apr 12 20:52:33 2007
Info: Elapsed time: 00:00:02
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