clk_div.tan.rpt

自己编写的任意分频VHDL程序

Timing Analyzer report for clk_div
Thu Apr 12 20:52:33 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clock'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                          ;
+------------------------------+-------+---------------+----------------------------------+-------+---------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From  ; To      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------+---------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 8.864 ns                         ; temp2 ; clk_out ; clock      ; --       ; 0            ;
; Clock Setup: 'clock'         ; N/A   ; None          ; 222.92 MHz ( period = 4.486 ns ) ; a2[3] ; a2[4]   ; clock      ; clock    ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;       ;         ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-------+---------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                               ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From  ; To    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 222.92 MHz ( period = 4.486 ns )               ; a2[3] ; a2[4] ; clock      ; clock    ; None                        ; None                      ; 4.225 ns                ;
; N/A   ; 227.63 MHz ( period = 4.393 ns )               ; a2[1] ; a2[4] ; clock      ; clock    ; None                        ; None                      ; 4.132 ns                ;
; N/A   ; 228.68 MHz ( period = 4.373 ns )               ; a2[4] ; a2[4] ; clock      ; clock    ; None                        ; None                      ; 4.112 ns                ;
; N/A   ; 229.04 MHz ( period = 4.366 ns )               ; a1[0] ; a2[2] ; clock      ; clock    ; None                        ; None                      ; 1.922 ns                ;
; N/A   ; 231.43 MHz ( period = 4.321 ns )               ; a2[3] ; a2[3] ; clock      ; clock    ; None                        ; None                      ; 4.060 ns                ;
; N/A   ; 236.52 MHz ( period = 4.228 ns )               ; a2[1] ; a2[3] ; clock      ; clock    ; None                        ; None                      ; 3.967 ns                ;
; N/A   ; 237.64 MHz ( period = 4.208 ns )               ; a2[4] ; a2[3] ; clock      ; clock    ; None                        ; None                      ; 3.947 ns                ;
; N/A   ; 239.41 MHz ( period = 4.177 ns )               ; a2[2] ; a2[4] ; clock      ; clock    ; None                        ; None                      ; 3.916 ns                ;
; N/A   ; 241.20 MHz ( period = 4.146 ns )               ; a2[0] ; a2[4] ; clock      ; clock    ; None                        ; None                      ; 3.885 ns                ;
; N/A   ; 241.37 MHz ( period = 4.143 ns )               ; a2[3] ; a2[1] ; clock      ; clock    ; None                        ; None                      ; 3.882 ns                ;
; N/A   ; 242.48 MHz ( period = 4.124 ns )               ; a1[1] ; a2[2] ; clock      ; clock    ; None                        ; None                      ; 1.801 ns                ;
; N/A   ; 243.55 MHz ( period = 4.106 ns )               ; a1[0] ; a2[4] ; clock      ; clock    ; None                        ; None                      ; 1.792 ns                ;
; N/A   ; 246.55 MHz ( period = 4.056 ns )               ; a2[3] ; a2[2] ; clock      ; clock    ; None                        ; None                      ; 3.795 ns                ;
; N/A   ; 246.91 MHz ( period = 4.050 ns )               ; a2[1] ; a2[1] ; clock      ; clock    ; None                        ; None                      ; 3.789 ns                ;
; N/A   ; 248.14 MHz ( period = 4.030 ns )               ; a2[4] ; a2[1] ; clock      ; clock    ; None                        ; None                      ; 3.769 ns                ;
; N/A   ; 249.25 MHz ( period = 4.012 ns )               ; a2[2] ; a2[3] ; clock      ; clock    ; None                        ; None                      ; 3.751 ns                ;
; N/A   ; 251.19 MHz ( period = 3.981 ns )               ; a2[0] ; a2[3] ; clock      ; clock    ; None                        ; None                      ; 3.720 ns                ;
; N/A   ; 252.33 MHz ( period = 3.963 ns )               ; a2[1] ; a2[2] ; clock      ; clock    ; None                        ; None                      ; 3.702 ns                ;
; N/A   ; 253.61 MHz ( period = 3.943 ns )               ; a2[4] ; a2[2] ; clock      ; clock    ; None                        ; None                      ; 3.682 ns                ;
; N/A   ; 255.10 MHz ( period = 3.920 ns )               ; a1[2] ; a2[3] ; clock      ; clock    ; None                        ; None                      ; 1.699 ns                ;
; N/A   ; 256.81 MHz ( period = 3.894 ns )               ; a1[4] ; a2[4] ; clock      ; clock    ; None                        ; None                      ; 1.686 ns                ;
; N/A   ; 258.33 MHz ( period = 3.871 ns )               ; a2[3] ; a2[0] ; clock      ; clock    ; None                        ; None                      ; 3.610 ns                ;
; N/A   ; 259.07 MHz ( period = 3.860 ns )               ; a1[1] ; a2[4] ; clock      ; clock    ; None                        ; None                      ; 1.669 ns                ;
; N/A   ; 260.69 MHz ( period = 3.836 ns )               ; a1[1] ; a2[3] ; clock      ; clock    ; None                        ; None                      ; 1.657 ns                ;
; N/A   ; 260.82 MHz ( period = 3.834 ns )               ; a2[2] ; a2[1] ; clock      ; clock    ; None                        ; None                      ; 3.573 ns                ;