254646.txt

数码管动态扫描 vhdl

文件头:
--功能：动态扫描模块，位选信号高电平有效;

ieee library;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity fpgaqudongleddongtai is

       port(clk:in std_logic;

            reset:in std_logic;

            din1:in std_logic_vector(6 downto 0);

            din2:in std_logic_vector(6 downto 0);

            din3:in std_logic_vector(6 downto 0);

            din4:in std_logic_vector(6 downto 0);

            shift:out std_logic_vector(3 downto 0);

            bus4:out std_logic_vecotor(6 downto 0));

end;

architecture behave of fpgaqudongleddongtai is 

       signal scan_clk:std_logic_vector(1 downto 0);--jizhuzaijiegoutizhixia

       begin

         process(clk,scan_clk,reset)

         variable scan:std_logic_vector(17 downto 0);--jizhuzaijinchengzhixia

         begin

           if reset='1' then 

               scan:="000000000000000000";

               scan_clk<="00";

           elsif  clk'event and clk='1' then 

      

文件尾:
         scan:=scan+1;

           end if ;

           scan_clk<=scan(17 downto 16);

         end process;

         begin

         case scan_clk is 

           when "00"=>

                bus4<=din1;

                shift<="0001";

           when "01"=>

                bus4<=din2;

                shift<="0010";

           when "10"=>

                bus4<=din3;

                shift<="0100";

           when "11"=>

                bus4<=din4;

                shift<="1000";

           when others=> bus4<="0000000";shift<="0000";

           end case ;

           end process;

end;

         
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