lancelot_fifo.vhd

基于FPGA的VGA控制器设计。对外支持普通VGA接口

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-- Lancelot Line Buffer Fifo  --
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-- Written by Marco Groeneveld --
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-- Histrory
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-- v2.0 : Updated for Nios II
-- v1.7 : changed reset polarity
-- v1.6 : Added line length 
-- v1.5 : Look ahead read status
-- v1.4 : Pipeline wrdata & wrreq
-- v1.3 : look ahead write status 
-- v1.2 : Instantiated dual-port ram 
-- v1.1 : Removed extra write registers
-- v0.1 : Initial version
---------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY lancelot_fifo IS
GENERIC(
		fifo_depth : natural := 8;
		fifo_width : natural := 32 		
	);
PORT(
		RST, WPRST, RPRST			: IN std_logic;
		WRCLK, RDCLK				: IN std_logic;
		WRREQ, RDREQ				: IN std_logic;
		WRDATA					: IN std_logic_vector(fifo_width - 1 DOWNTO 0);
		RDDATA					: OUT std_logic_vector(fifo_width - 1 DOWNTO 0);
		WPTOP, WPBOTTOM, RPTOP, RPBOTTOM	: OUT std_logic;
		LINE_LENGTH				: IN std_logic_vector(10 DOWNTO 0)
	);
END lancelot_fifo;

ARCHITECTURE behavior OF lancelot_fifo IS

COMPONENT lancelot_dpram_256x32
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		wraddress	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		wrclock		: IN STD_LOGIC ;
		rdclock		: IN STD_LOGIC ;
		wr_aclr		: IN STD_LOGIC  := '0';
		rd_aclr		: IN STD_LOGIC  := '0';
		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
END COMPONENT;

SIGNAL wrdata_int : std_logic_vector(fifo_width - 1 DOWNTO 0);
SIGNAL wrreq_int : std_logic; 
SIGNAL wp_s, rp_s : std_logic_vector(7 DOWNTO 0);
SIGNAL wp, rp : integer RANGE 0 TO 256;
SIGNAL wr_line_length, rd_line_length : integer RANGE 0 TO 256;
SIGNAL wptop_int, wpbottom_int, rptop_int, rpbottom_int : std_logic;

BEGIN

-- Misc
WPTOP <= wptop_int;
WPBOTTOM <= wpbottom_int;
RPTOP <= rptop_int;
RPBOTTOM <= rpbottom_int;

dpram : lancelot_dpram_256x32 
	PORT MAP (
			wr_aclr 	=> RST,  
			rd_aclr		=> RST, 
			data	 	=> wrdata_int,
			wraddress	=> wp_s,
			rdaddress 	=> rp_s,
			wren	 	=> wrreq_int,
			wrclock	 	=> WRCLK,
			rdclock	 	=> RDCLK,
			q	 	=> RDDATA
		);

-- Pipeline wrdata and wrreq
PROCESS(RST, WRCLK, WRDATA, WRREQ)
BEGIN
	IF RST = '1' THEN
    		wrdata_int <= (others => '0');
 		wrreq_int <= '0';
	ELSIF (WRCLK'event AND WRCLK = '1') THEN
		wrdata_int <= WRDATA;
		wrreq_int <= WRREQ;
	END IF;
END PROCESS;

-- Synchronisation line length
PROCESS(RST, WRCLK, LINE_LENGTH)
BEGIN
	IF RST = '1' THEN
    		wr_line_length <= 0;
	ELSIF (WRCLK'event AND WRCLK = '1') THEN
		wr_line_length <= (conv_integer(LINE_LENGTH)/4);
	END IF;
END PROCESS;

PROCESS(RST, RDCLK, LINE_LENGTH)
BEGIN
	IF RST = '1' THEN
    		rd_line_length <= 0;
	ELSIF (RDCLK'event AND RDCLK = '1') THEN
		rd_line_length <= (conv_integer(LINE_LENGTH)/4);
	END IF;
END PROCESS;
 
-- Write pointer mechanisme
PROCESS(RST, WRCLK, wrreq_int, WPRST, wptop_int, wp)
--	VARIABLE wp : integer RANGE 0 TO 160;
BEGIN
	IF (RST = '1' OR WPRST = '1') THEN
		wp <= 0;
		wptop_int <= '0';
  		wpbottom_int <= '1';
	ELSIF (WRCLK'event AND WRCLK = '1') THEN
		IF wp = (wr_line_length - 6) THEN
			wptop_int <= '1';
	   	END IF;
	   	IF (wrreq_int = '1' AND wp < wr_line_length) THEN
			wp <= wp + 1;
			wpbottom_int <= '0';
		END IF;
	
 	END IF;
wp_s <= conv_std_logic_vector(wp, 8);
END PROCESS;

-- Read pointer mechanisme
PROCESS(RST, RDCLK, RDREQ, RPRST, rptop_int, rp)
--	VARIABLE rp : integer RANGE 0 TO 160;
BEGIN
	IF (RST = '1' OR  RPRST = '1') THEN
		rp <= 0;
		rptop_int <= '0';
  		rpbottom_int <= '1';
  		rp_s <= (others => '0');
	ELSIF (RDCLK'event AND RDCLK = '1') THEN
		IF rp = (rd_line_length - 1) THEN
			rptop_int <= '1';
		END IF;
		IF (RDREQ = '1' AND rp < rd_line_length) THEN
			rp <= rp + 1;
			rpbottom_int <= '0';
			rp_s <= conv_std_logic_vector(rp, 8);
		END IF;
  	END IF;

END PROCESS;

END behavior;