class.ptf

基于FPGA的VGA控制器设计。对外支持普通VGA接口

###
# Lancelot VGA class.ptf
# Written by Marco Groeneveld
# For more information and updates please visit http://www.fpga.nl
###
CLASS magic_avalon_lancelot_vga
{
	ASSOCIATED_FILES
	{
		Add_Program = "advert";
		Edit_Program = "advert";
		Generator_Program = "mk_lancelot_vga.pl";
	}
	MODULE_DEFAULTS
	{
		class = "magic_avalon_lancelot_vga";
		class_version = "4.0";
		SYSTEM_BUILDER_INFO
		{
			Instantiate_In_System_Module = "1";
			Is_Enabled = "1";
			Date_Modified = "--unknown--";
		}
		WIZARD_SCRIPT_ARGUMENTS
		{
		}
		PORT_WIRING
		{
			PORT video_clk
			{
				width = "1";
				direction = "input";
				type = "export";
			}
			PORT r
			{
				width = "8";
				direction = "output";
				type = "export";
			}
			PORT g
			{
				width = "8";
				direction = "output";
				type = "export";
			}
			PORT b
			{
				width = "8";
				direction = "output";
				type = "export";
			}
			PORT hs
			{
				width = "1";
				direction = "output";
				type = "export";
			}
			PORT vs
			{
				width = "1";
				direction = "output";
				type = "export";
			}
			PORT m1
			{
				width = "1";
				direction = "output";
				type = "export";
			}
			PORT m2
			{
				width = "1";
				direction = "output";
				type = "export";
			}
			PORT blank_n
			{
				width = "1";
				direction = "output";
				type = "export";
			}
			PORT sync_n
			{
				width = "1";
				direction = "output";
				type = "export";
			}
			PORT sync_t
			{
				width = "1";
				direction = "output";
				type = "export";
			}
		}        
		SLAVE vga_avalon_slave
		{
			SYSTEM_BUILDER_INFO
			{
				Bus_Type = "avalon";
				Has_IRQ = "0";
				Address_Width = "3";
				Data_Width = "32";
				Address_Alignment = "native";
				Is_Enabled = "1";
			}
			PORT_WIRING
			{
				PORT avalon_slave_data_out
				{
					direction = "output";
					width = "32";
					type = "readdata";
				}
				PORT avalon_slave_cs
				{
					direction = "input";
					width = "1";
					type = "chipselect";
				}
				PORT avalon_slave_data_in
				{
					direction = "input";
					width = "32";
					type = "writedata";
				}
				PORT avalon_slave_addr
				{
					direction = "input";
					width = "3";
					type = "address";
				}
				PORT avalon_slave_wr
				{
					direction = "input";
					width = "1";
					type = "write";
				}
				PORT avalon_slave_rd
				{
					direction = "input";
					width = "1";
					type = "read";
				}
			}
		}
		MASTER vga_avalon_master
		{
			SYSTEM_BUILDER_INFO
			{
				Bus_Type = "avalon";
				Address_Width = "32";
				Max_Address_Width = "32";
				Data_Width = "32";
				Is_Enabled = "1";
			}
			PORT_WIRING
			{
				PORT reset
				{
					direction = "input";
					width = "1";
					type = "reset";
				}
				PORT avalon_clk
				{
					direction = "input";
					width = "1";
					type = "clk";
				}
				PORT avalon_master_addr
				{
					direction = "output";
					width = "32";
					type = "address";
				}
				PORT avalon_master_data_in
				{
					direction = "input";
					width = "32";
					type = "readdata";
				}
				PORT avalon_master_rd
				{
					direction = "output";
					width = "1";
					type = "read";
				}
				PORT avalon_master_waitreq
				{
					direction = "input";
					width = "1";
					type = "waitrequest";
				}
				PORT avalon_master_lock
				{
					direction = "output";
					width = "1";
					type = "arbiterlock";
				}
			}
		}
	}
	USER_INTERFACE
	{
		USER_LABELS
		{
			name = "Lancelot VGA";
			technology = "Lancelot";
		}
		WIZARD_UI advert
		{
			title="Lancelot VGA - {{ $MOD }}";
			align = "center";
			IMAGE
			{
				file="and_gate.gif";
				url="http://www.fpga.nl";
			}
			TEXT
			{
				layout="flow";
				title="<p style=\"font: 14 arial; font-weight: bold; text-align: center\">Lancelot VGA Peripheral.</p>";
				font="bold";
			}
			TALLY
			{
				LE="850";
				ESB="6";
			}
			TEXT
			{
				title="<p style=\"text-align: center\">VGA peripheral for Nios.
				<br>It displays an image with a maximum resolution of 800 * 600 image with 256 colors. 
				<br>For more information and updates please visit 
				<a href=\"http://www.fpga.nl\"
				>http://www.fpga.nl</a></p>";
			}
		}
	}
	DEFAULT_GENERATOR
	{
		top_module_name = "lancelot_vga";
		black_box = "0";
		vhdl_synthesis_files = "lancelot_vga.vhd"; 
		verilog_synthesis_files = "";
		black_box_files = "";
	}
}