📄 tiny16_maxii.drc.rpt
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; Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in receiving clock domain ; On ;
; Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ;
; Only one VREF pin should be assigned to HardCopy test pin in an I/O bank (This rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; Off ;
; PLL drives multiple clock network types (This rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; Off ;
; Design is missing fmax requirement ; Off ;
; Design is missing tco, tpd, or tsu requirement ; Off ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+---------------------------------------------------+
; Design Assistant Results Summary ;
+----------------------------+----------------------+
; Severity of Rule violation ; Number of violations ;
+----------------------------+----------------------+
; Critical ; 2 ;
; High ; 2 ;
; Medium ; 1 ;
; Information only ; 58 ;
+----------------------------+----------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Critical ;
+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+
; Rule name ; Name ;
+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+
; Combinational logic used as clock signal should be implemented according to Altera standard scheme ; flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|ufm_drclk ;
; Combinational logic used as clock signal should be implemented according to Altera standard scheme ; flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|ufm_arclk ;
+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------+
; High ;
+----------------------------------------+-------------------------------------------------------------------------------------------+
; Rule name ; Name ;
+----------------------------------------+-------------------------------------------------------------------------------------------+
; Clock signal should be a global signal ; flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|ufm_drclk ;
; Clock signal should be a global signal ; flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|ufm_arclk ;
+----------------------------------------+-------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Medium ;
+---------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+
; Rule name ; Name ;
+---------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+
; Clock signal source should drive only input clock ports ; flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|wire_maxii_ufm_block1_osc ;
+---------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Information only ;
+---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+---------+
; Rule name ; Name ; Fan-Out ;
+---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+---------+
; Nodes with more than specified number of fan-outs ; flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|wire_maxii_ufm_block1_osc ; 224 ;
; Nodes with more than specified number of fan-outs ; tiny16:cpu|fsm.exec_2 ; 47 ;
; Nodes with more than specified number of fan-outs ; tiny16:cpu|fsm.exec_1 ; 94 ;
; Nodes with more than specified number of fan-outs ; tiny16:cpu|ir[10] ; 42 ;
; Nodes with more than specified number of fan-outs ; tiny16:cpu|ir[9] ; 44 ;
; Nodes with more than specified number of fan-outs ; tiny16:cpu|reduce_nor~26 ; 36 ;
; Nodes with more than specified number of fan-outs ; tiny16:cpu|ir[0] ; 41 ;
; Nodes with more than specified number of fan-outs ; tiny16:cpu|reduce_nor~28 ; 35 ;
; Top nodes with highest fan-out ; flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|wire_maxii_ufm_block1_osc ; 224 ;
; Top nodes with highest fan-out ; tiny16:cpu|fsm.exec_1 ; 94 ;
; Top nodes with highest fan-out ; tiny16:cpu|fsm.exec_2 ; 47 ;
; Top nodes with highest fan-out ; tiny16:cpu|ir[9] ; 44 ;
; Top nodes with highest fan-out ; tiny16:cpu|ir[10] ; 42 ;
; Top nodes with highest fan-out ; tiny16:cpu|ir[0] ; 41 ;
; Top nodes with highest fan-out ; tiny16:cpu|reduce_nor~26 ; 36 ;
; Top nodes with highest fan-out ; tiny16:cpu|reduce_nor~28 ; 35 ;
; Top nodes with highest fan-out ; tiny16:cpu|reduce_nor~40 ; 30 ;
; Top nodes with highest fan-out ; tiny16:cpu|ir[14] ; 28 ;
; Top nodes with highest fan-out ; tiny16:cpu|ir[15] ; 28 ;
; Top nodes with highest fan-out ; tiny16:cpu|reduce_nor~33 ; 25 ;
; Top nodes with highest fan-out ; tiny16:cpu|ir[11] ; 24 ;
; Top nodes with highest fan-out ; tiny16:cpu|ir[8] ; 23 ;
; Top nodes with highest fan-out ; tiny16:cpu|reduce_nor~21 ; 21 ;
; Top nodes with highest fan-out ; tiny16:cpu|address[15]~1598 ; 20 ;
; Top nodes with highest fan-out ; tiny16:cpu|reduce_nor~27 ; 20 ;
; Top nodes with highest fan-out ; tiny16:cpu|data_out[0]~612 ; 18 ;
; Top nodes with highest fan-out ; tiny16:cpu|ir[3] ; 18 ;
; Top nodes with highest fan-out ; tiny16:cpu|ir_ena~0 ; 18 ;
; Top nodes with highest fan-out ; flash:flash|UFM:flash|UFM_altufm_parallel_pej:UFM_altufm_parallel_pej_component|in_read_drclk~216 ; 17 ;
; Top nodes with highest fan-out ; reduce_nor~1014 ; 17 ;
; Top nodes with highest fan-out ; tiny16:cpu|ra_data[2]~4923 ; 17 ;
; Top nodes with highest fan-out ; tiny16:cpu|fsm.fetch ; 16 ;
; Top nodes with highest fan-out ; tiny16:cpu|sp[14]~672 ; 16 ;
; Top nodes with highest fan-out ; tiny16:cpu|alu_b[15]~1232 ; 16 ;
; Top nodes with highest fan-out ; tiny16:cpu|sp_ena~205 ; 16 ;
; Top nodes with highest fan-out ; tiny16:cpu|sp[14]~836 ; 16 ;
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