sdram hy57v6416et.vhd

现代的4bank*1M*16bit的SDRAM（HY57V6416ET）的VHDL行为仿真程序

          when ACT =>
            BankActivateFlag <= TRUE;
            NextState := READ;
          when PCG =>
-- EDIT
--          PrechargeFlag <= TRUE;
--          if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
--              (BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
-- EDIT
            PrechargeFlag <= TRUE;
            IMSIBA <= (BA1, BA0);
            if (BankActivatedFlag(conv_integer(IMSIBA)) = '1') then
              if (((BankActivatedFlag = "0001") and (BankActivatedFlag(conv_integer(IMSIBA)) = '1'))
                  or ((BankActivatedFlag = "0010") and (BankActivatedFlag(conv_integer(IMSIBA)) = '1'))
                  or ((BankActivatedFlag = "0100") and (BankActivatedFlag(conv_integer(IMSIBA)) = '1'))
                  or ((BankActivatedFlag = "1000") and (BankActivatedFlag(conv_integer(IMSIBA)) = '1'))) then
                NextState := IDLE;
              else
                NextState := RACT;
              end if;
            end if;
          when PCGA =>
            PrechargeAllFlag <= TRUE;
            NextState := IDLE;
          when BSTOP =>
            BurstStopFlag <= transport TRUE after (ModeRegister.CAS_LATENCY - 1)*clk_cycle,
                                       FALSE after (ModeRegister.CAS_LATENCY)*clk_cycle;
-- EDIT
--          if (WriteFlag = FALSE) then
              NextState := RACT;
--          end if;
          when CSPND =>
            NextState := RDSPND;
          when NOP =>
            NextState := READ;
          when CKEEXIT =>
            NextState := READ;
          when others =>
            assert false report
            "NOTE : (6STATE_MACHINE) : Illegal Command Issued. Command Ignored."
            severity note;
        end case;
        if ((CurrentCommand /= RD) and (NextState = READ) and (ReadFinFlag = TRUE)) then
          NextState := RACT;
        end if;
      when RDSPND =>
        if (CurrentCommand = CKEEXIT) then
          NextState := READ;
        elsif (CurrentCommand = NOP) then
          NextState := RDSPND;
        else
          assert false report
          "NOTE : (STATE_MACHINE) : Command ignored"
          severity note;
          NextState := RDSPND;
        end if;
      when WRITE =>
        case CurrentCommand is
          when MRS =>
            last_mrs_set <= transport now after 1 ns;
            OpCode := Adr_bus(NUM_OF_ROW_ADD-1 downto 0);  --?
            MODE_REGISTER_SET (OpCode, MR);
            MROpCode <= OpCode;
            ModeRegister <= MR;
          when RD =>
            ReadFlag <= TRUE;
            Read_CA <= '1';
            NextState := READ;
          when RDA =>
            ApCount := 0;
            ReadFlag <= TRUE;
            Read_CA <= '1';
            EXEBA <= (BA1, BA0);
            NextState := READA;
          when WR =>
            WriteFlag <= TRUE;
            Write_CA <= '1';
            NextState := WRITE;
          when WRA =>
            ApCount := 0;
            WriteFlag <= TRUE;
            Write_CA <= '1';
            EXEBA <= (BA1, BA0);
            NextState := WRITEA;
          when ACT =>
            BankActivateFlag <= TRUE;
            NextState := WRITE;
          when PCG =>
-- EDIT
--          PrechargeFlag <= TRUE;
--          if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
--              (BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
-- EDIT
            PrechargeFlag <= TRUE;
            IMSIBA <= (BA1, BA0);
            if (BankActivatedFlag(conv_integer(IMSIBA)) = '1') then
              if (((BankActivatedFlag = "0001") and (BankActivatedFlag(conv_integer(IMSIBA)) = '1'))
                  or ((BankActivatedFlag = "0010") and (BankActivatedFlag(conv_integer(IMSIBA)) = '1'))
                  or ((BankActivatedFlag = "0100") and (BankActivatedFlag(conv_integer(IMSIBA)) = '1'))
                  or ((BankActivatedFlag = "1000") and (BankActivatedFlag(conv_integer(IMSIBA)) = '1'))) then
                NextState := IDLE;
              else
                NextState := RACT;
              end if;
            end if;
          when PCGA =>
            PrechargeAllFlag <= TRUE;
            NextState := IDLE;
          when BSTOP =>
            BurstStopFlag <= transport TRUE, FALSE after clk_cycle;
-- EDIT
--          if (ReadFlag = FALSE) then
              NextState := RACT;
--          end if;
          when CSPND =>
            NextState := WRSPND;
          when NOP =>
            NextState := WRITE;
          when CKEEXIT =>
            NextState := WRITE;
          when others =>
            assert false report
            "NOTE : (7STATE_MACHINE) : Illegal Command Issued. Command Ignored."
            severity note;
        end case;
        if ((CurrentCommand /= WR) and (NextState = WRITE) and (WriteFinFlag = TRUE)) then
          NextState := RACT;
        end if;
      when WRSPND =>
        if (CurrentCommand = CKEEXIT) then
          NextState := WRITE;
        elsif (CurrentCommand = NOP) then
          NextState := WRSPND;
        else
          assert false
          report "NOTE : (STATE_MACHINE) : Command ignored"
          severity note;
          NextState := WRSPND;
        end if;
      when others =>
        assert false report
        "ERROR : (STATE_MACHINE) : Impossible State" severity error;
        NextState := ERROR;
      end case;
  else
  end if;
  if (CLK_INT'EVENT and CLK_INT = '0') then
    if (Read_CA = '1') then
      Read_CA <= '0';
    end if;
    if (Write_CA = '1') then
      Write_CA <= '0';
    end if;
  end if;
  if ((bstop_write'EVENT and bstop_write = '1') or (WriteFinFlag'EVENT and WriteFinFlag = TRUE) or
      (PCG_WriteFin'EVENT and PCG_WriteFin = '1')) then
    WriteFlag <= FALSE;
  end if;
  if (BankActivateFinFlag = TRUE) then
    BankActivateFlag <= FALSE after 2 ns;
  end if;
  if (PrechargeFinFlag = TRUE) then
    PrechargeFlag <= FALSE after 5 ns;
  end if;
  if (ReadFinFlag'EVENT and ReadFinFlag = TRUE) then
    ReadFlag <= FALSE;
    if (CurrentState /= READA) then
      if (BankActivatedFlag = "0000") then
        NextState := IDLE;
-- EDIT
--    else
--      NextState := RACT;
      elsif (WriteFlag = FALSE) then
        NextState := RACT;
      end if;
    end if;
  end if;
  if (PrechargeAllFinFlag = TRUE) then
    PrechargeAllFlag <= FALSE after 5 ns;
  end if;
  if (SelfRefExtFlag = TRUE) then
    SelfRefFlag <= FALSE after 2 ns;
  end if;
  if (BankActivatedFlag'EVENT) then
    if (BankActivatedFlag = "0000") then
      NextState := IDLE;
    end if;
  end if;
  CurrentState <= NextState;
end process; 
----------------------------------------------------------------------------------
--------STATE_MACHINE

----------------------------------------------------------------------------------
------------MEMORY_BANK_ACTIVATE_PRECHARGE
MEMORY_BANK_ACTIVATE_PRECHARGE : process (BankActivateFlag, CLK_INT, PrechargeFlag, AutoPrechargeFlag, PrechargeAllFlag)

variable BA : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
variable RA : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'X');
variable SenseAmpArray : SA_ARRAY_TYPE;
variable DATA : std_logic_vector ((WORD_SIZE - 1) downto 0) := (others => 'X');
variable SA : SA_TYPE;
variable TMP_BUF : std_logic_vector ((WORD_SIZE - 1) downto 0) := (others => '0');
variable i, j, l, u : integer := 0;
variable MEM_CELL_ARRAY0, MEM_CELL_ARRAY1 : MEM_CELL_TYPE;
variable MEM_CELL_ARRAY2, MEM_CELL_ARRAY3 : MEM_CELL_TYPE;

begin
  if (BankActivateFlag'EVENT and BankActivateFlag = TRUE) Then
    BA := (BA1, BA0); 
    BankActivatedFlag(conv_integer(BA)) <= '1';
  End if;
  if (CLK_INT'EVENT and CLK_INT = '0') then
    if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans0 = '1'))) Then
      tmp_act_trans0 <= '0';
    end if;
    if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans1 = '1'))) Then
      tmp_act_trans1 <= '0';
    end if;
    if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans2 = '1'))) Then
      tmp_act_trans2 <= '0';
    end if;
    if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans3 = '1'))) Then
      tmp_act_trans3 <= '0';
    end if;
  end if;
  if (BankActivateFlag'EVENT and BankActivateFlag = TRUE) then
    BA := (BA1, BA0);
    RA := Adr_bus(NUM_OF_ROW_ADD-1 downto 0); --?
    i := 0;
    j := 0;
    u := 0;
    if (BankActivatedFlag (conv_integer (BA)) = '1') then
      assert false report
      "WARNING : (MEMORY_BANK_ACTIVATE) : Activating same bank without precharge. Command Ignored."
      severity warning;
      BankActivateFinFlag <= transport TRUE, FALSE after 2 ns;
    elsif (BankActivatedFlag (conv_integer (BA)) = '0') then
      if (now - refresh_check(conv_integer(BA), conv_integer(RA)) > 64000000 ns) then
        assert false report
        "WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms. So, This Row's Data Is Lost." 
        severity warning;  
      end if;    
      case BA is 
        when "00" =>
          b0_last_activate <= transport now after (tRAS (Part_number) - 1 ns);
          RA_Activated_B0 <= RA;
        when "01" =>
          b1_last_activate <= transport now after (tRAS (Part_number) - 1 ns);
          RA_Activated_B1 <= RA;
        when "10" =>
          b2_last_activate <= transport now after (tRAS (Part_number) - 1 ns);
          RA_Activated_B2 <= RA;
        when "11" =>
          b3_last_activate <= transport now after (tRAS (Part_number) - 1 ns);
          RA_Activated_B3 <= RA;
        when others =>
          assert false report
          "WARNING : (MEMORY_BANK_ACTIVATE) : Impossible Bank Address"
          severity warning;
      end case;
      if (conv_integer (BA) = 0) then
        if (MEM_CELL_ARRAY0(conv_integer (RA)) = NULL) then
          MEM_CELL_ARRAY0(conv_integer (RA)) := NEW ROW_DATA_TYPE;
          loop
            exit when u >= NUM_OF_COLS;
            MEM_CELL_ARRAY0(conv_integer (RA))(u) := 0;
            u := u + 1;
          end loop;
        end if;
        loop
          exit when i >= NUM_OF_COLS;
          TMP_BUF := conv_std_logic_vector(MEM_CELL_ARRAY0 (conv_integer (RA))(i), WORD_SIZE);
          j := 0;
          loop
            exit when j >= WORD_SIZE;
            SA_ARRAY_A0(i, j) <= TMP_BUF(j);
            j := j + 1;
          end loop;
          i := i + 1;
        end loop;
        tmp_act_trans0 <= '1';
      elsif (conv_integer (BA) = 1) then
        if (MEM_CELL_ARRAY1(conv_integer (RA)) = NULL) then
          MEM_CELL_ARRAY1(conv_integer (RA)) := NEW ROW_DATA_TYPE;
          loop
            exit when u >= NUM_OF_COLS;
            MEM_CELL_ARRAY1(conv_integer (RA))(u) := 0;
            u := u + 1;
          end loop;
        end if;
        loop
          exit when i >= NUM_OF_COLS;
          TMP_BUF := conv_std_logic_vector(MEM_CELL_ARRAY1 (conv_integer (RA))(i), WORD_SIZE);
          j := 0;
          loop
            exit when j >= WORD_SIZE;
            SA_ARRAY_A1(i, j) <= TMP_BUF(j);
            j := j + 1;
          end loop;
          i := i + 1;
        end loop;
        tmp_act_trans1 <= '1';
      elsif (conv_integer (BA) = 2) then
        if (MEM_CELL_ARRAY2(conv_integer (RA)) = NULL) then
          MEM_CELL_ARRAY2(conv_integer (RA)) := NEW ROW_DATA_TYPE;
          loop
            exit when u >= NUM_OF_COLS;
            MEM_CELL_ARRAY2(conv_integer (RA))(u) := 0;
            u := u + 1;
          end loop;
        end if;
        loop
          exit when i >= NUM_OF_COLS;
          TMP_BUF := conv_std_logic_vector(MEM_CELL_ARRAY2 (conv_integer (RA))(i), WORD_SIZE);
          j := 0;
          loop
            exit when j >= WORD_SIZE;
            SA_ARRAY_A2(i, j) <= TMP_BUF(j);
            j := j + 1;
          end loop;
          i := i + 1;
        end loop;
        tmp_act_trans2 <= '1';
      elsif (conv_integer (BA) = 3) then
        if (MEM_CELL_ARRAY3(conv_integer (RA)) = NULL) then
          MEM_CELL_ARRAY3(conv_integer (RA)) := NEW ROW_DATA_TYPE;
          loop
            exit when u >= NUM_OF_COLS;
            MEM_CELL_ARRAY3(conv_integer (RA))(u) := 0;
            u := u + 1;
          end loop;
        end if;
        loop
          exit when i >= NUM_OF_COLS;
          TMP_BUF := conv_std_logic_vector(MEM_CELL_ARRAY3 (conv_integer (RA))(i), WORD_SIZE);
          j := 0;
          loop
            exit when j >= WORD_SIZE;
            SA_ARRAY_A3(i, j) <= TMP_BUF(j);
            j := j + 1;
          end loop;
          i := i + 1;
        end loop;
        tmp_act_trans3 <= '1';
      end if;
      BankActivateFinFlag <= tra