📄 sdram hy57v6416et.vhd
字号:
NextState := IDLE;
else
NextState := RACT;
end if;
else
NextState := WRITEA;
end if;
last_mrs_set <= transport now after 1 ns;
OpCode := Adr_bus(NUM_OF_ROW_ADD-1 downto 0); --?
MODE_REGISTER_SET (OpCode, MR);
MROpCode <= OpCode;
ModeRegister <= MR;
when RD =>
if (EXEBA = (BA1, BA0)) then
ApCount := 0;
else
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
else
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after clk_cycle, FALSE after clk_cycle + 2 ns;
ApCount := 0;
end if;
end if;
ReadFlag <= TRUE;
Read_CA <= '1';
NextState := READ;
when WR =>
if (EXEBA = (BA1, BA0)) then
ApCount := 0;
else
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
else
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after clk_cycle, FALSE after clk_cycle + 2 ns;
ApCount := 0;
end if;
end if;
WriteFlag <= TRUE;
Write_CA <= '1';
NextState := WRITE;
when RDA =>
if (EXEBA = (BA1, BA0)) then
ApCount := 0;
else
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
else
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after clk_cycle, FALSE after clk_cycle + 2 ns;
ApCount := 0;
end if;
end if;
ReadFlag <= TRUE;
Read_CA <= '1';
EXEBA <= (BA1, BA0);
NextState := READA;
when WRA =>
if (EXEBA = (BA1, BA0)) then
ApCount := 0;
else
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
else
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after clk_cycle, FALSE after clk_cycle + 2 ns;
ApCount := 0;
end if;
end if;
WriteFlag <= TRUE;
Write_CA <= '1';
EXEBA <= (BA1, BA0);
NextState := WRITEA;
when PCG =>
if (EXEBA = (BA1, BA0)) then
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after (PrevModeRegister.BURST_LENGTH - ApCount)*clk_cycle,
FALSE after (PrevModeRegister.BURST_LENGTH - ApCount)*clk_cycle + 2 ns;
ApCount := 0;
else
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
NextState := IDLE;
else
NextState := WRITEA;
end if;
end if;
PrechargeFlag <= TRUE;
when PCGA =>
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after (PrevModeRegister.BURST_LENGTH - ApCount)*clk_cycle,
FALSE after (PrevModeRegister.BURST_LENGTH - ApCount)*clk_cycle + 2 ns;
ApCount := 0;
PrechargeAllFlag <= TRUE;
NextState := IDLE;
when ACT =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
NextState := RACT;
else
NextState := WRITEA;
end if;
BankActivateFlag <= TRUE;
when BSTOP =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
else
AutoPrechargeFlag <= transport TRUE after clk_cycle, FALSE after clk_cycle + 2 ns;
BurstStopFlag <= transport TRUE, FALSE after clk_cycle;
end if;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
ApCount := 0;
when CSPND =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
end if;
NextState := WRASPND;
when NOP =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
else
NextState := WRITEA;
end if;
when CKEEXIT =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
ApCount := 0;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
else
NextState := WRITEA;
end if;
when others =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
else
NextState := WRITEA;
end if;
assert false report
"NOTE : (3STATE_MACHINE) : Illegal Command Issued. Command Ignored."
severity note;
end case;
when WRASPND =>
if (CurrentCommand = CKEEXIT) then
if (BankActivatedFlag(conv_integer(EXEBA)) = '1') then
NextState := WRITEA;
else
if (BankActivatedFlag = "0000") then
NextState := IDLE;
else
NextState := RACT;
end if;
end if;
elsif (CurrentCommand = NOP) then
NextState := WRASPND;
else
assert false report
"NOTE : (STATE_MACHINE) : Command ignored"
severity note;
NextState := WRASPND;
end if;
when CLKSPND =>
if (CurrentCommand = CKEEXIT) then
NextState := IDLE;
elsif (CurrentCommand = NOP) then
NextState := CLKSPND;
else
assert False
report "NOTE : (4STATE_MACHINE) : Illegal Command Issued. Command Ignored."
severity note;
end if;
when SLFREF =>
if (CurrentCommand = CKEEXIT) then
SelfRefExtFlag <= transport TRUE, FALSE after clk_cycle + 2 ns;
last_sr_ext <= transport now after 1 ns;
NextState := IDLE;
elsif (CurrentCommand = NOP) then
SelfRefFlag <= TRUE;
NextState := SLFREF;
else
assert false
report "NOTE : (STATE_MACHINE) : Command ignored"
severity note;
NextState := SLFREF;
end if;
when PWRDN =>
if (CurrentCommand = CKEEXIT) then
PcgPwrDnExtFlag <= TRUE;
last_pd_ext <= transport now after 1 ns;
NextState := IDLE;
elsif (CurrentCommand = NOP) then
PcgPwrDnFlag <= TRUE;
NextState := PWRDN;
else
assert false
report "NOTE : (STATE_MACHINE) : Command ignored"
severity note;
NextState := SLFREF;
end if;
when RACT =>
case CurrentCommand is
when MRS =>
last_mrs_set <= transport now after 1 ns;
OpCode := Adr_bus(NUM_OF_ROW_ADD-1 downto 0); --?
MODE_REGISTER_SET (OpCode, MR);
MROpCode <= OpCode;
ModeRegister <= MR;
when CSPND =>
ActPwrDnFlag <= TRUE;
NextState := ACTSPND;
when ACT =>
BankActivateFlag <= TRUE;
NextState := RACT;
when RD =>
ReadFlag <= TRUE;
Read_CA <= '1';
NextState := READ;
when RDA =>
ApCount := 0;
ReadFlag <= TRUE;
Read_CA <= '1';
EXEBA <= (BA1, BA0);
NextState := READA;
when WR =>
WriteFlag <= TRUE;
Write_CA <= '1';
NextState := WRITE;
when WRA =>
ApCount := 0;
WriteFlag <= TRUE;
Write_CA <= '1';
EXEBA <= (BA1, BA0);
NextState := WRITEA;
when PCG =>
PrechargeFlag <= TRUE;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
when PCGA =>
PrechargeAllFlag <= TRUE;
NextState := IDLE;
when NOP =>
NextState := RACT;
when AREF =>
NextState := RACT;
when others =>
assert false
report "NOTE : (5STATE_MACHINE) : Illegal Command Issued. Command Ignored."
severity note;
end case;
when ACTSPND =>
if (CurrentCommand = CKEEXIT) then
ActPwrDnExtFlag <= transport TRUE, FALSE after 2 ns;
NextState := RACT;
elsif (CurrentCommand = NOP) then
ActPwrDnFlag <= transport TRUE, FALSE after 2 ns;
NextState := ACTSPND;
else
assert false
report "NOTE : (STATE_MACHINE) : Command ignored"
severity note;
NextState := ACTSPND;
end if;
when READ =>
case CurrentCommand is
when MRS =>
last_mrs_set <= transport now after 1 ns;
OpCode := Adr_bus(NUM_OF_ROW_ADD-1 downto 0); --?
MODE_REGISTER_SET (OpCode, MR);
MROpCode <= OpCode;
ModeRegister <= MR;
when RD =>
ReadFlag <= TRUE; -- after 1 ns; -- trying to fix it here
Read_CA <= '1';
NextState := READ;
when RDA =>
ApCount := 0;
ReadFlag <= TRUE;
Read_CA <= '1';
EXEBA <= (BA1, BA0);
NextState := READA;
when WR =>
-- EDIT
-- WriteFlag <= TRUE after 2.5 ns;
WriteFlag <= TRUE;
Write_CA <= '1';
NextState := WRITE;
when WRA =>
ApCount := 0;
-- EDIT
-- WriteFlag <= TRUE after 2.5 ns;
WriteFlag <= TRUE;
Write_CA <= '1';
EXEBA <= (BA1, BA0);
NextState := WRITEA;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -