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i := 0;
j := 0;
if (tmp_ref_addr1'event) then
refresh_check (0, conv_integer(tmp_ref_addr1((NUM_OF_ROW_ADD - 1) downto 0))) <= now;
refresh_check (1, conv_integer(tmp_ref_addr1((NUM_OF_ROW_ADD - 1) downto 0))) <= now;
refresh_check (2, conv_integer(tmp_ref_addr1((NUM_OF_ROW_ADD - 1) downto 0))) <= now;
refresh_check (3, conv_integer(tmp_ref_addr1((NUM_OF_ROW_ADD - 1) downto 0))) <= now;
elsif (tmp_ref_addr2'event) then
refresh_check (conv_integer(tmp_ref_addr2(1 downto 0)),
conv_integer(tmp_ref_addr2((NUM_OF_ROW_ADD + NUM_OF_BANK_ADD - 1) downto 2))) <= now;
end if;
end
process;--------------------------------------------------------------------------
-------------REFRESH_TIME_CHECK
--------------------------------------------------------------------------------CKE(-1) AND CKE(0) SIGNAL EVALUATION
CKE_EVAL : process (CLK)
begin
if (CLK'EVENT and CLK = '0' and CLK'LAST_VALUE = '1') then
CKEN(-1) <= CKEN(0);
elsif (CLK'EVENT and CLK = '1' and CLK'LAST_VALUE = '0') then
CKEN(0) <= CKE;
end if;
end
process;--------------------------------------------------------------------CKE(-1) AND CKE(0) SIGNAL EVALUATION
----------------------------------------------------------------------------------
---------------------STATE_MACHINE
STATE_MACHINE : process (PCG_WriteFin, WriteFinFlag, CLK, CLK_INT, CKE,
BankActivateFinFlag, PrechargeFinFlag, PrechargeAllFinFlag, SelfRefExtFlag,
BankActivatedFlag, ReadFinFlag, bstop_write)
variable ApCount : integer := 0;
variable ChipSelectBar : std_logic := '0';
variable RowAddrStrobeBar : std_logic := '0';
variable ColAddrStrobeBar : std_logic := '0';
variable WriteEnableBar : std_logic := '0';
variable Address10 : std_logic := '0';
variable ClockEnable : CKE_TYPE := (others => '0');
variable NextState : STATE_TYPE := IDLE;
variable CurrentCommand : COMMAND_TYPE := NOP;
variable OpCode : MROPCODE_TYPE := (others => 'X');
variable MR : MODE_REGISTER;
variable BA : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
variable BankActFlag : std_logic_vector((NUM_OF_BANKS - 1) downto 0) := (others => '0');
begin
if (CLK = '1' and CLK'EVENT and CLK'LAST_VALUE = '0') then
BA := (BA1, BA0);
ClockEnable(-1) := CKEN(-1);
ClockEnable(0) := CKE;
if ClockEnable (-1) = '1' then
ChipSelectBar := CSB;
RowAddrStrobeBar := RASB;
ColAddrStrobeBar := CASB;
WriteEnableBar := WEB;
Address10 := Adr_bus(idx_ap_in_ra); --?
BankActFlag := BankActivatedFlag;
end if;
COMMAND_DECODE (ChipSelectBar, RowAddrStrobeBar, ColAddrStrobeBar,
WriteEnableBar, Address10, ClockEnable, CurrentCommand, BankActFlag);
case CurrentState is
when IDLE =>
case CurrentCommand is
when MRS =>
assert (PUSCheckFinFlag = TRUE) report
"ERROR : (STATE_MACHINE) : Initialization with Power Up Sequence Error!"
severity error;
ModeRegisterSetFlag <= FALSE;
last_mrs_set <= transport now after 1 ns;
OpCode := Adr_bus(NUM_OF_ROW_ADD-1 downto 0); --?
MODE_REGISTER_SET (OpCode, MR);
MROpCode <= OpCode;
ModeRegister <= MR;
ModeRegisterSetFlag <= TRUE;
NextState := IDLE;
when PD =>
PcgPwrDnFlag <= TRUE;
NextState := PWRDN;
when SREF =>
SelfRefFlag <= TRUE;
NextState := SLFREF;
when ACT =>
BankActivateFlag <= TRUE;
NextState := RACT;
when AREF =>
AutoRefFlag <= TRUE, FALSE after 2 ns;
NextState := IDLE;
when NOP =>
NextState := IDLE;
when PCGA =>
PrechargeAllFlag <= TRUE;
NextState := IDLE;
when PCG =>
PrechargeFlag <= TRUE;
NextState := IDLE;
when CSPND =>
NextState := CLKSPND;
when RD|RDA =>
Read_CA <= '1';
ReadFlag <= TRUE;
NextState := READ;
when WR|WRA =>
Write_CA <= '1';
WriteFlag <= TRUE;
NextState := WRITE;
when others =>
assert false
report "NOTE : (1STATE_MACHINE) : Illegal Command Issued. Command Ignored."
severity note;
end case;
when READA =>
ApCount := ApCount + 1;
case CurrentCommand is
when MRS =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
else
NextState := READA;
end if;
last_mrs_set <= transport now after 1 ns;
OpCode := Adr_bus(NUM_OF_ROW_ADD-1 downto 0); --?
MODE_REGISTER_SET (OpCode, MR);
MROpCode <= OpCode;
ModeRegister <= MR;
when RD =>
if (EXEBA = (BA1, BA0)) then
ApCount := 0;
else
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
else
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after clk_cycle, FALSE after clk_cycle + 2 ns;
ApCount := 0;
end if;
end if;
ReadFlag <= TRUE;
Read_CA <= '1';
NextState := READ;
when WR =>
if (EXEBA = (BA1, BA0)) then
ApCount := 0;
else
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
else
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after clk_cycle, FALSE after clk_cycle + 2 ns;
ApCount := 0;
end if;
end if;
-- EDIT
-- WriteFlag <= TRUE after 2.5 ns;
WriteFlag <= TRUE;
Write_CA <= '1';
NextState := WRITE;
when RDA =>
if (EXEBA = (BA1, BA0)) then
ApCount := 0;
else
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
else
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after clk_cycle, FALSE after clk_cycle + 2 ns;
ApCount := 0;
end if;
end if;
ReadFlag <= TRUE;
Read_CA <= '1';
EXEBA <= (BA1, BA0);
NextState := READA;
when WRA =>
if (EXEBA = (BA1, BA0)) then
ApCount := 0;
else
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
else
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after clk_cycle, FALSE after clk_cycle + 2 ns;
ApCount := 0;
end if;
end if;
-- EDIT
-- WriteFlag <= TRUE after 2.5 ns;
WriteFlag <= TRUE;
Write_CA <= '1';
EXEBA <= (BA1, BA0);
NextState := WRITEA;
when PCG =>
if (EXEBA = (BA1, BA0)) then
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after (PrevModeRegister.BURST_LENGTH - ApCount)*clk_cycle,
FALSE after (PrevModeRegister.BURST_LENGTH - ApCount)*clk_cycle + 2 ns;
ApCount := 0;
else
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
NextState := IDLE;
else
NextState := READA;
end if;
end if;
PrechargeFlag <= TRUE;
when PCGA =>
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE after (PrevModeRegister.BURST_LENGTH - ApCount)*clk_cycle,
FALSE after (PrevModeRegister.BURST_LENGTH - ApCount)*clk_cycle + 2 ns;
ApCount := 0;
PrechargeAllFlag <= TRUE;
NextState := IDLE;
when ACT =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
NextState := RACT;
else
NextState := READA;
end if;
BankActivateFlag <= TRUE;
when BSTOP =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
else
AutoPrechargeFlag <= transport TRUE after clk_cycle, FALSE after clk_cycle + 2 ns;
BurstStopFlag <= transport TRUE after (ModeRegister.CAS_LATENCY - 1)*clk_cycle,
FALSE after (ModeRegister.CAS_LATENCY)*clk_cycle;
end if;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
ApCount := 0;
when CSPND =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
end if;
NextState := RDASPND;
when NOP =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
else
NextState := READA;
end if;
when CKEEXIT =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
else
NextState := READA;
end if;
when others =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
NextState := IDLE;
else
NextState := RACT;
end if;
else
NextState := READA;
end if;
assert false report
"NOTE : (2STATE_MACHINE) : Illegal Command Issued. Command Ignored."
severity note;
end case;
when RDASPND =>
if (CurrentCommand = CKEEXIT) then
if (BankActivatedFlag(conv_integer(EXEBA)) = '1') then
NextState := READA;
else
if (BankActivatedFlag = "0000") then
NextState := IDLE;
else
NextState := RACT;
end if;
end if;
elsif (CurrentCommand = NOP) then
NextState := RDASPND;
else
assert false report
"NOTE : (STATE_MACHINE) : Command ignored"
severity note;
NextState := RDASPND;
end if;
when WRITEA =>
ApCount := ApCount + 1;
case CurrentCommand is
when MRS =>
if (ApCount = PrevModeRegister.BURST_LENGTH) then
APBA <= EXEBA;
AutoPrechargeFlag <= transport TRUE, FALSE after 2 ns;
ApCount := 0;
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
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