sdram hy57v6416et.vhd

现代的4bank*1M*16bit的SDRAM（HY57V6416ET）的VHDL行为仿真程序

        elsif (MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '1') then
          MR.BURST_LENGTH := 8;
        elsif (MROPCODE(2) = '1' and MROPCODE(1) = '1' and MROPCODE(0) = '1') then
          MR.BURST_LENGTH := NUM_OF_COLS; --? FP
        else
          assert false report
          "ERROR : (MODE_REGISTER_SET) Used Reserved Value in BURST_LENGTH!"
          severity error;
        end if;
      else
        assert false report
        "WARNING : (MODE_REGISTER_SET) : The Values of A7 Must be '0' in MRS Command."
        severity WARNING;
      end if;
    end MODE_REGISTER_SET;
----------------------------------------------------------------------------------
--------------
  function CHAR_TO_STD_LOGIC (
    c : in character)
    return std_logic is
    variable r : std_logic;
  begin
    case c is
      when '0' => r := '0';
      when 'L' => r := 'L';
      when '1' => r := '1';
      when 'H' => r := 'H';
      when 'W' => r := 'W';
      when 'Z' => r := 'Z';
      when 'U' => r := 'U';
      when '-' => r := '-';
      when others => r := 'X';
    end case;
    return r;
  end CHAR_TO_STD_LOGIC;
----------------------------------------------------------------------------------
--------------
  function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT is
    variable Result: BIT;
  begin
    case V is
      when '0' | 'L' =>
        Result := '0';
      when '1' | 'H' =>
        Result := '1';
      when 'X' | 'W' | 'Z' | 'U' | '-' =>
        Result := '0';
    end case;
    return Result;
  end STD_LOGIC_TO_BIT;
----------------------------------------------------------------------------------
--------------
  function REMAINDER (val0 : in integer; val1 : in integer) return integer is
    variable Result : integer;
  begin
    Result := val0;
    loop
      exit when Result < val1;
      Result := Result - val1;
    end loop;
    return Result;
  end REMAINDER;
----------------------------------------------------------------------------------
--------------
  function XOR_FUNC (val0 : in std_logic_vector; val1 : in std_logic_vector) 
return std_logic_vector is
    variable Result : std_logic_vector(2 downto 0);
    variable j : integer := 0;
  begin
    for i in val0'RANGE LOOP
      if (val0(i) /= val1(i)) then
        Result(i) := '1';
      else
        Result(i) := '0';
      end if;
      j := j + 1;
    end loop;
    return Result((j - 1) downto 0);
  end XOR_FUNC;
----------------------------------------------------------------------------------
--------------    
  procedure MEMORY_READ_ith_ROW (
    variable BA : in std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
    variable cur_CA : in std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0) := (others => 'X');
    variable Data : out DATA_TYPE;
    variable SenseAmpArray : in SA_ARRAY_TYPE) is
      variable j : integer := 0;
      variable SenseAmp : SA_TYPE;
  begin
    SenseAmp := SenseAmpArray (conv_integer (BA));
    loop
      Data (j)
        := SenseAmp (conv_integer (cur_CA), j);
      j := j + 1;
      if (j >= WORD_SIZE) then
        exit;
      end if;
    end loop;
  end MEMORY_READ_ith_ROW;
----------------------------------------------------------------------------------
--------------
  procedure MEMORY_WRITE_a_ROW (
    variable BA : in std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
    variable cur_CA : in std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0) := (others => 'X');
    variable WriteDriverArray : in SA_ARRAY_TYPE;
    variable SenseAmpArray : out SA_ARRAY_TYPE) is
      variable j : integer := 0;
      variable SenseAmp : SA_TYPE;
      variable WriteDriver : SA_TYPE;
  begin
    loop
      SenseAmp (conv_integer (cur_CA), j)
        := WriteDriverArray (conv_integer (BA))(conv_integer (cur_CA), j);
      j := j + 1;
      if (j >= WORD_SIZE) then
        exit;
      end if;
    end loop;
    SenseAmpArray (conv_integer (BA)) := SenseAmp;
  end MEMORY_WRITE_a_ROW;
----------------------------------------------------------------------------------
end SDRAM_PACK;

----------------------------------------------------------------------
---------------------------------------
LIBRARY IEEE;
USE STD.textio.all;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_MISC.all;
USE IEEE.STD_LOGIC_TEXTIO.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
USE WORK.SDRAM_PACK.all; --?
USE work.en_arith.ALL;

----------------------------------------------------------------------------------
---------------------------------------
Entity HY57V6416ET is --? device name
  Generic (
    Part_Number : PART_NUM_TYPE := T7);
  Port (  
          CLK     :  in      std_logic;
          CKE     :  in      std_logic;
          CSB     :  in      std_logic;
          RASB    :  in      std_logic;
          CASB    :  in      std_logic;
          WEB     :  in      std_logic;
          DQM     :  in      std_logic;

          BA1     :  in      std_logic;
          BA0     :  in      std_logic;

          Adr_bus :  in      std_logic_vector(NUM_OF_ROW_ADD-1 downto 0);

          DQ_bus  :  inout   std_logic_vector(WORD_SIZE-1 downto 0) := creat_hiz_vect(WORD_SIZE)
          );
End HY57V6416ET;
----------------------------------------------------------------------------------
---------------------------------------
Architecture Behavioral_Model of HY57V6416ET is

signal ReadFix : integer := 4;
signal real_CA1 : std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0);
signal M1 : integer;
signal Din1 : std_logic_vector((WORD_SIZE-1) DOWNTO 0);
signal DATA1 : std_logic_vector((WORD_SIZE-1) DOWNTO 0);
signal WRITEDRIVEARRAR_CHECK0 : std_logic_vector((WORD_SIZE-1) DOWNTO 0);
signal WRITEDRIVEARRAR_CHECK1 : std_logic_vector((WORD_SIZE-1) DOWNTO 0);
signal WRITEDRIVEARRAR_CHECK2 : std_logic_vector((WORD_SIZE-1) DOWNTO 0);
signal CLKY : std_logic;
signal cur_time : time := 0 ns;
signal bstop_write : std_logic := '0';
signal Ref_time, clk_cycle_rising : time := 0 ns;
signal tmp_act_trans0, tmp_act_trans1, tmp_act_trans2, tmp_act_trans3, RefCnt_trans : std_logic := '0';
signal PCG_WriteFin, PCG_ReadFin1, PCG_ReadFin2 : std_logic := '0';
signal CLK_INT_DLY : std_logic := '0';
signal tmp_ref_addr1 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
signal tmp_ref_addr2 : std_logic_vector((NUM_OF_ROW_ADD + NUM_OF_BANK_ADD - 1) downto 0) := (others => '0');
signal RefChkTimeInit : boolean := FALSE;
signal refresh_check : REF_CHECK;
signal real_col_addr : std_logic_vector((NUM_OF_COL_ADD - 1) downto 0) := (others => '0');
signal CKE_last_zero : std_logic := '0';
signal CLK_INT : std_logic := '0';
signal Read_CA, Write_CA : std_logic := '0';
signal d_mask1, d_mask2 : std_logic := '0';
signal DQtransaction, tmp_w_trans0, tmp_w_trans1, tmp_w_trans2, tmp_w_trans3 : std_logic := '0';
signal RA_Activated_B0 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
signal RA_Activated_B1 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
signal RA_Activated_B2 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
signal RA_Activated_B3 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
signal APBA, EXEBA, IMSIBA : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'U'); --?
signal CKEN : CKE_TYPE := (others => '1');
signal SA_ARRAY : SA_ARRAY_TYPE;
signal SA_ARRAY_A0 : SA_TYPE;
signal SA_ARRAY_A1 : SA_TYPE;
signal SA_ARRAY_A2 : SA_TYPE;
signal SA_ARRAY_A3 : SA_TYPE;
signal SA_ARRAY_W0 : SA_TYPE;
signal SA_ARRAY_W1 : SA_TYPE;
signal SA_ARRAY_W2 : SA_TYPE;
signal SA_ARRAY_W3 : SA_TYPE;
signal WD_ARRAY : SA_ARRAY_TYPE;
signal RefCnt : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
signal Clk_Cycle_Chk : boolean := FALSE;
signal ModeRegisterSetFlag : boolean := FALSE;
signal ModeRegisterFlag : boolean := FALSE;
signal BankActivateFlag : boolean := FALSE;
signal BankActivateFinFlag : boolean := FALSE;
signal BankActivatedFlag : std_logic_vector ((NUM_OF_BANKS - 1) downto 0) := (others => '0');
signal ReadFlag : boolean := FALSE;
signal WriteFlag : boolean := FALSE;
signal DataQueue : PIPE_TYPE;
signal PrechargeFlag : boolean := FALSE;
signal AutoPrechargeFlag : boolean := FALSE;
signal PrechargeFinFlag : boolean := FALSE;
signal PrechargeAllFlag : boolean := FALSE;
signal PrechargeAllFinFlag : boolean := FALSE;
signal ReadFinFlag : boolean := FALSE;
signal WriteFinFlag : boolean := FALSE;
signal BurstStopFlag : boolean := FALSE;
signal AutoRefFlag : boolean := FALSE;
signal SelfRefFlag : boolean := FALSE;
signal SelfRefExtFlag : boolean := FALSE;
signal PUSCheckFinFlag : boolean := FALSE;
signal PcgPwrDnFlag : boolean := FALSE;
signal PcgPwrDnExtFlag : boolean := FALSE;
signal ActPwrDnFlag : boolean := FALSE;
signal ActPwrDnExtFlag : boolean := FALSE;
signal CurrentReadBurstIndex : integer := 0;
signal CurrentWriteBurstIndex : integer := 0;
signal CurrentState : STATE_TYPE := IDLE;
signal MROpCode : MROPCODE_TYPE := (others => 'U');
signal ModeRegister, PrevModeRegister : MODE_REGISTER := (          
  WRITE_MODE => BRBW, --? maximum CL value
  CAS_LATENCY => 3,
  BURST_MODE => SEQUENTIAL,
  BURST_LENGTH => 4
  );
signal CLKStableFlag : boolean := FALSE;
signal last_aref_time : time := 0 ns;
signal clk_cycle : time := 0 ns;
signal clk_last_rising : time := 0 ns;
signal clk_last_falling : time := 0 ns;
signal b0_last_activate : time := 0 ns;
signal b1_last_activate : time := 0 ns;
signal b2_last_activate : time := 0 ns;
signal b3_last_activate : time := 0 ns;
signal b0_last_precharge : time := 0 ns;
signal b1_last_precharge : time := 0 ns;
signal b2_last_precharge : time := 0 ns;
signal b3_last_precharge : time := 0 ns;
signal b0_last_column_access : time := 0 ns;
signal b1_last_column_access : time := 0 ns;
signal b2_last_column_access : time := 0 ns;
signal b3_last_column_access : time := 0 ns;
signal b0_last_data_in : time := 0 ns;
signal b1_last_data_in : time := 0 ns;
signal b2_last_data_in : time := 0 ns;
signal b3_last_data_in : time := 0 ns;
signal last_mrs_set : time := 0 ns;
signal last_data_in : time := 0 ns;
signal last_pd_ext : time := 0 ns;
signal last_sr_ext : time := 0 ns;
signal tCCD : time := 0 ns;
signal tDPL : time := 0 ns;
signal tDAL : time := 0 ns;
signal tMRD : time := 0 ns;
signal tPDE : time := 0 ns;
signal tSRE : time := 0 ns;
signal cke_ch : time := 0 ns;
signal rasb_ch : time := 0 ns;
signal casb_ch : time := 0 ns;
signal web_ch : time := 0 ns;
signal csb_ch : time := 0 ns;
signal dqm_ch : time := 0 ns;
signal ba0_ch : time := 0 ns;
signal ba1_ch : time := 0 ns;
TYPE time_array IS ARRAY (INTEGER RANGE <>) OF time;
signal adr_bus_ch : time_array(NUM_OF_ROW_ADD-1 downto 0) := (others => 0 ns);
signal dq_bus_ch : time_array(WORD_SIZE-1 downto 0) := (others => 0 ns);
Begin

----------------------------------------------------------------------------------
------------------------------------
CLK_CYCLE_CHECK : process(CLK)----------------------------------------------------------------------
---CLK_CYCLE_CHECK

begin
  if (Clk_Cycle_Chk = FALSE) then
    if (CLK'EVENT and CLK = '1') then
      if (clk_cycle_rising = 0 ns) then
        clk_cycle_rising <= now;
      else
        clk_cycle <= now - clk_cycle_rising;
        Clk_Cycle_Chk <= TRUE;
      end if;
    end if;
  end if;
end 
Process;--------------------------------------------------------------------------
-----------------CLK_CYCLE_CHECK INT_CLK_GENERATION : 
process(CLK)
-------------------------------------------------------------------INT_CLK_GENERATION

begin
  if (CLK'EVENT and CLK = '1' and CLK'LAST_VALUE = '0') then
    if (CKE = '1' and CKE_last_zero = '0') then
      CLK_INT <= '1';
    elsif (CKE = '1' and CKE_last_zero = '1') then
      CLK_INT <= '0';
      CKE_last_zero <= '0';
    elsif (CKE = '0' and CKE_last_zero = '0') then
      CLK_INT <= '1';
      CKE_last_zero <= '1';
    elsif (CKE = '0' and CKE_last_zero = '1') then
      CLK_INT <= '0';
      CKE_last_zero <= '1'; 
    end if;
  elsif (CLK'EVENT and CLK = '0' and CLK'LAST_VALUE = '1') then
    CLK_INT <= '0';
  end if;
end 
Process;
--------------------------------------------------------------------------
-------------INT_CLK_GENERATION    

CLK_INT_DLY <= CLK_INT after 2 ns;

REFRESH_TIME_CHECK : process(tmp_ref_addr1, tmp_ref_addr2)
-----------------------------------------REFRESH_TIME_CHECK

variable i, j : integer := 0;

begin
  if (RefChkTimeInit = FALSE) then
    loop
      exit when (i > (NUM_OF_BANKS - 1));
      j := 0;
      loop
        exit when (j >= NUM_OF_ROWS);
        refresh_check (i, j) <= 0 ns;
        j := j + 1;
      end loop;
      i := i + 1;
    end loop;
    RefChkTimeInit <= TRUE;
  end if;