sdram hy57v6416et.vhd

现代的4bank*1M*16bit的SDRAM（HY57V6416ET）的VHDL行为仿真程序

LIBRARY IEEE;
USE STD.textio.all;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_MISC.all;
USE IEEE.STD_LOGIC_TEXTIO.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

package SDRAM_PACK is

  constant NUM_OF_ROW_ADD : integer := 12;

  constant NUM_OF_COL_ADD : integer := 8; --?

  constant NUM_OF_BANK_ADD : integer := 2;

  constant WORD_SIZE : integer := 16; --?

  constant idx_ap_in_ra : integer := 10;

  constant NUM_OF_ROWS : integer := 2**NUM_OF_ROW_ADD;

  constant NUM_OF_COLS : integer := 2**NUM_OF_COL_ADD;

  constant NUM_OF_BANKS : integer := 2**NUM_OF_BANK_ADD;

  constant NUM_OF_PIPES : integer := 2; --?

  type PART_NUM_TYPE is (T6, K, H, T7, T8, P, S);

  type PART_NUM is array (T6 to S) of time;

  constant tCK3 : PART_NUM := (T6=>6 ns, K=>7.5 ns, H=>7.5 ns, T7=>7 ns, T8=>8 ns, P=>10 ns, S=>10 ns);

  constant tCK2 : PART_NUM := (T6=>10 ns, K=>7.5 ns, H=>10 ns, T7=>10 ns, T8=>10 ns, P=>10 ns, S=>12 ns);

  constant tCK1 : time := 24 ns;

  constant tCHW : PART_NUM := (T6=>2.5 ns, K=>2.5 ns, H=>2.5 ns, T7=>2.0 ns, T8=>3 ns, P=>3 ns, S=>3 ns);

  constant tCLW : PART_NUM := (T6=>2.5 ns, K=>2.5 ns, H=>2.5 ns, T7=>2.0 ns, T8=>3 ns, P=>3 ns, S=>3 ns);

  constant tAC3 : PART_NUM := (T6=>5.4 ns, K=>5.4 ns, H=>5.4 ns, T7=>5.4 ns, T8=>6 ns, P=>6 ns, S=>6 ns);

  constant tAC2 : PART_NUM := (T6=>6 ns, K=>5.4 ns, H=>6 ns, T7=>6.0 ns, T8=>6 ns, P=>6 ns, S=>6 ns);

  constant tAC1 : PART_NUM := (T6=>16 ns, K=>12.9 ns, H=>16 ns, T7=>16 ns, T8=>16 ns, P=>16 ns, S=>18 ns);

  constant tOH : PART_NUM := (T6=>2.7 ns, K=>2.7 ns, H=>2.7 ns, T7=>2.5 ns, T8=>3 ns, P=>3 ns, S=>3 ns);

  constant tDS : PART_NUM := (T6=>1.5 ns, K=>1.5 ns, H=>1.5 ns, T7=>1.5 ns, T8=>2 ns, P=>2 ns, S=>2 ns);

  constant tDH : PART_NUM := (T6=>0.8 ns, K=>0.8 ns, H=>0.8 ns, T7=>0.8 ns, T8=>1 ns, P=>1 ns, S=>1 ns);

  constant tAS : PART_NUM := (T6=>1.5 ns, K=>1.5 ns, H=>1.5 ns, T7=>1.5 ns, T8=>2 ns, P=>2 ns, S=>2 ns);

  constant tAH : PART_NUM := (T6=>0.8 ns, K=>0.8 ns, H=>0.8 ns, T7=>0.8 ns, T8=>1 ns, P=>1 ns, S=>1 ns);

  constant tCKS : PART_NUM := (T6=>1.5 ns, K=>1.5 ns, H=>1.5 ns, T7=>1.5 ns, T8=>2 ns, P=>2 ns, S=>2 ns);

  constant tCKH : PART_NUM := (T6=>0.8 ns, K=>0.8 ns, H=>0.8 ns, T7=>0.8 ns, T8=>1 ns, P=>1 ns, S=>1 ns);

  constant tCS : PART_NUM := (T6=>1.5 ns, K=>1.5 ns, H=>1.5 ns, T7=>1.5 ns, T8=>2 ns, P=>2 ns, S=>2 ns);

  constant tCH : PART_NUM := (T6=>0.8 ns, K=>0.8 ns, H=>0.8 ns, T7=>0.8 ns, T8=>1 ns, P=>1 ns, S=>1 ns);

  constant tRC : PART_NUM := (T6=>60 ns, K=>60 ns, H=>65 ns, T7=>63 ns, T8=>68 ns, P=>70 ns, S=>70 ns);

  constant tRRC : PART_NUM := (T6=>60 ns, K=>65 ns, H=>65 ns, T7=>63 ns, T8=>68 ns, P=>70 ns, S=>70 ns);

  constant tRCD : PART_NUM := (T6=>18 ns, K=>15 ns, H=>20 ns, T7=>20 ns, T8=>20 ns, P=>20 ns, S=>20 ns);

  constant tRAS : PART_NUM := (T6=>42 ns, K=>45 ns, H=>45 ns, T7=>42 ns, T8=>48 ns, P=>50 ns, S=>50 ns);

  constant tRASmax : PART_NUM := (T6=>100000 ns, K=>100000 ns, H=>100000 ns, T7=>100000 ns, T8=>100000 ns,
                                  P=>100000 ns, S=>100000 ns);

  constant tRP : PART_NUM := (T6=>18 ns, K=>15 ns, H=>20 ns, T7=>20 ns, T8=>20 ns, P=>20 ns, S=>20 ns);

  constant tRRD : PART_NUM := (T6=>12 ns, K=>15 ns, H=>15 ns, T7=>14 ns, T8=>16 ns, P=>20 ns, S=>20 ns);

  constant tREF : PART_NUM := (T6=>64 ms , K=>64 ms, H=>64 ms, T7=>64 ms, T8=>64 ms, P=>64 ms, S=>64 ms);

  constant tPUS : time := 200 us;

  type STATE_TYPE is (
    PWRDN,
    SLFREF,
    IDLE,
    ACTSPND,
    RDSPND,
    WRSPND,
    RACT,
    READ,
    READA,
    WRITE,
    WRITEA,
    CLKSPND,
    WRASPND,
    RDASPND,
    ERROR);

  type COMMAND_TYPE is (
    NOP,
    MRS,
    ACT,
    RD,
    RDA,
    WR,
    WRA,
    PCG,
    PCGA,
    BSTOP,
    AREF,
    SREF,
    PD,
    CSPND,
    CKEEXIT,
    ILLEGAL,
    ERROR);

  type BURST_MODE_TYPE is (
    SEQUENTIAL,
    INTERLEAVE);

  type WRITE_MODE_TYPE is (
    BRBW,
    BRSW);

  subtype CL_TYPE is integer range 1 to 3;

  subtype BL_TYPE is integer range 1 to NUM_OF_COLS;

  type MODE_REGISTER is 
    record
      CAS_LATENCY : CL_TYPE;
      BURST_MODE : BURST_MODE_TYPE;
      BURST_LENGTH : BL_TYPE;
      WRITE_MODE : WRITE_MODE_TYPE;
    end record;

  type REF_CHECK is array (0 to (NUM_OF_BANKS - 1), 0 to (NUM_OF_ROWS - 1)) of time;

  type SA_TYPE is array (0 to (NUM_OF_COLS - 1), (WORD_SIZE - 1) downto 0) of std_logic;

  type SA_ARRAY_TYPE is array (0 to (NUM_OF_BANKS - 1)) of SA_TYPE;

  type BANK_TYPE is array (0 to (NUM_OF_ROWS - 1)) of SA_TYPE;

  subtype DATA_SIZE is integer range 0 to (2**WORD_SIZE - 1); --? x4/x8/x16/x32

  type ROW_DATA_TYPE is array (0 to (NUM_OF_COLS - 1)) of DATA_SIZE;

  type RAM_PNTR is ACCESS ROW_DATA_TYPE;

  type CELL_ARRAY_TYPE is array (0 to (NUM_OF_ROWS - 1), 0 to (NUM_OF_COLS - 1)) of DATA_SIZE;

  type MEM_CELL_TYPE is array (0 to (NUM_OF_ROWS - 1)) of RAM_PNTR; 

  subtype DATA_TYPE is std_logic_vector ((WORD_SIZE - 1) downto 0);

  type PIPE_TYPE is array (0 to NUM_OF_PIPES) of DATA_TYPE;

  type CKE_TYPE is array (integer range -1 to 0) of std_logic;
 
  subtype MROPCODE_TYPE is std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0);

  subtype COL_ADD_TYPE is std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0);

  procedure COMMAND_DECODE (
    variable
      CSB,
      RASB,
      CASB,
      WEB,
      AP : in std_logic;
    variable
      CKE : in CKE_TYPE;
    variable
      COMMAND : out COMMAND_TYPE;
    variable
      BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0));

  procedure MEMORY_READ_ith_ROW (
    variable BA : in std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
    variable cur_CA : in std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0) := (others => 'X');
    variable Data : out DATA_TYPE;
    variable SenseAmpArray : in SA_ARRAY_TYPE);

  procedure MEMORY_WRITE_a_ROW (
    variable BA : in std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
    variable cur_CA : in std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0) := (others => 'X');
    variable WriteDriverArray : in SA_ARRAY_TYPE;
    variable SenseAmpArray : out SA_ARRAY_TYPE);

  procedure MODE_REGISTER_SET (
    variable MROPCODE : in MROPCODE_TYPE;
    variable MR : out MODE_REGISTER);

  function CHAR_TO_STD_LOGIC (
    c : in character)
    return std_logic;

  function REMAINDER (
    val0 : in integer;
    val1 : in integer) return integer;

  function XOR_FUNC (
    val0 : in std_logic_vector;
    val1 : in std_logic_vector) return std_logic_vector;

  function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT;

end SDRAM_PACK; 
-------------------------------------------------------------------Sdram Package

package body SDRAM_PACK is
----------------------------------------------------------------------------------
--------------
  procedure COMMAND_DECODE (
    variable
      CSB,
      RASB,
      CASB,
      WEB,
      AP : in std_logic;
    variable
      CKE : in CKE_TYPE;
    variable
      COMMAND : out COMMAND_TYPE;
    variable
      BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0)) is

    begin
      case CKE (-1) is
        when '1' =>
          case CKE (0) is
            when '0' =>
              if (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='1') then
                COMMAND := SREF;
              elsif (((CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') or (CSB = '1')) and (BankState = "0000")) then
                COMMAND := PD;
              elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='0') then
                COMMAND := MRS;
              elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='1') then
                COMMAND := ACT;
              elsif ((CSB = '0' and RASB = '1' and CASB = '0' and WEB ='1') and (AP = '0')) then
                COMMAND := RD;
              elsif ((CSB = '0' and RASB = '1' and CASB = '0' and WEB ='1') and (AP = '1')) then
                COMMAND := RDA;
              elsif ((CSB = '0' and RASB = '1' and CASB = '0' and WEB ='0') and (AP = '0')) then
                COMMAND := WR;
              elsif ((CSB = '0' and RASB = '1' and CASB = '0' and WEB ='0') and (AP = '1')) then
                COMMAND := WRA;
              elsif ((CSB = '0' and RASB = '0' and CASB = '1' and WEB ='0') and (AP = '0')) then
                COMMAND := PCG;
              elsif ((CSB = '0' and RASB = '0' and CASB = '1' and WEB ='0') and (AP = '1')) then
                COMMAND := PCGA;
              elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='0') then
                COMMAND := BSTOP;
              else
                COMMAND := CSPND;
              end if;
            when '1' =>
              if (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='0') then
                COMMAND := MRS;
              elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1')) then
                COMMAND := NOP;
              elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='1') then
                COMMAND := ACT;
              elsif ((CSB = '0' and RASB = '1' and CASB = '0' and WEB ='1') and (AP = '0')) then
                COMMAND := RD;
              elsif ((CSB = '0' and RASB = '1' and CASB = '0' and WEB ='1') and (AP = '1')) then
                COMMAND := RDA;
              elsif ((CSB = '0' and RASB = '1' and CASB = '0' and WEB ='0') and (AP = '0')) then
                COMMAND := WR;
              elsif ((CSB = '0' and RASB = '1' and CASB = '0' and WEB ='0') and (AP = '1')) then
                COMMAND := WRA;
              elsif ((CSB = '0' and RASB = '0' and CASB = '1' and WEB ='0') and (AP = '0')) then
                COMMAND := PCG;
              elsif ((CSB = '0' and RASB = '0' and CASB = '1' and WEB ='0') and (AP = '1')) then
                COMMAND := PCGA;
              elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='0') then
                COMMAND := BSTOP;
              elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='1') then
                COMMAND := AREF;
              else
                COMMAND := ILLEGAL;
              end if;
            when others =>
              COMMAND := ERROR;
            end case;
        when '0' =>
          case CKE (0) is
            when '0' =>
              COMMAND := NOP;
            when '1' =>
              COMMAND := CKEEXIT;
            when others =>
              COMMAND := ERROR;
            end case;
        when others =>
          COMMAND := ERROR;
        end case;
    end COMMAND_DECODE;
----------------------------------------------------------------------------------
--------------
  procedure MODE_REGISTER_SET (
    variable MROPCODE : in MROPCODE_TYPE;
    variable MR : out MODE_REGISTER) is
    begin
      if (
--        MROPCODE(11) = '0' and
--        MROPCODE(10) = '0' and
          MROPCODE(7)  = '0') then
        if (MROPCODE(6) = '0' and MROPCODE(5) = '0' and MROPCODE(4) = '1') then
          MR.CAS_LATENCY := 1;
        elsif (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '0') then
          MR.CAS_LATENCY := 2;
        elsif (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '1') then
          MR.CAS_LATENCY := 3;
        else
          assert false report
          "ERROR : (MODE_REGISTER_SET) Used Reserved Value in CAS_LATENCY!"
          severity error;
        end if;
        if (MROPCODE(9) = '0' and MROPCODE(8) = '0') then
          MR.WRITE_MODE := BRBW;
        elsif (MROPCODE(9) = '1' and MROPCODE(8) = '0') then
          MR.WRITE_MODE := BRSW;
        else
          assert false report
          "ERROR : (MODE_REGISTER_SET) Used Reserved Value in WRITE_MODE!"
          severity error;
        end if;
        if (MROPCODE(3) = '0') then
          MR.BURST_MODE := SEQUENTIAL;
        else
          MR.BURST_MODE := INTERLEAVE;
        end if;
        if (MROPCODE(2) = '0' and MROPCODE(1) = '0' and MROPCODE(0) = '0') then
          MR.BURST_LENGTH := 1;
        elsif (MROPCODE(2) = '0' and MROPCODE(1) = '0' and MROPCODE(0) = '1') then
          MR.BURST_LENGTH := 2;
        elsif (MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '0') then
          MR.BURST_LENGTH := 4;