dss_ad50.s54
来自「使用在TI 系列dsk5402 的很多可用例子」· S54 代码 · 共 542 行 · 第 1/2 页
S54
542 行
;
; Copyright 2003 by Texas Instruments Incorporated.
; All rights reserved. Property of Texas Instruments Incorporated.
; Restricted rights to use, duplicate or disclose this code are
; granted through contract.
;
; @(#) XDAS 2.51.00 11-29-2003 (xdas-2.50.00.9)
;
;
; ======== dss_ad50.s54 ========
;
;
.mmregs
.text
;---------------------------------------------------------------------------
;
; Buffered serial port #0 and #1
;
;---------------------------------------------------------------------------
DRR2_0 .set 00020h ; McBSP 0 data receive register 2 (most significant)
DRR1_0 .set 00021h ; McBSP 0 data receive register 1 (least significant)
DXR2_0 .set 00022h ; McBSP 0 data transmit register 2 (most significant)
DXR1_0 .set 00023h ; McBSP 0 data transmit register 1 (least significant)
DRR2_1 .set 00040h ; McBSP 1 data receive register 2 (most significant)
DRR1_1 .set 00041h ; McBSP 1 data receive register 1 (least significant)
DXR2_1 .set 00042h ; McBSP 1 data transmit register 2 (most significant)
DXR1_1 .set 00043h ; McBSP 1 data transmit register 1 (least significant)
;
; Registers are accessed via base plus offset ( sub address )
;
SPSA0_a .set 00038h ; McBSP 0 serial port sub-address
SPAD0_a .set 00039h ; McBSP 0 serial port sub-addressed data
SPSA1_a .set 00048h ; McBSP 1 serial port sub-address
SPAD1_a .set 00049h ; McBSP 1 serial port sub-addressed data
SPCR1_sa .set 00000h
SPCR2_sa .set 00001h
RCR1_sa .set 00002h
RCR2_sa .set 00003h
XCR1_sa .set 00004h
XCR2_sa .set 00005h
SRGR1_sa .set 00006h
SRGR2_sa .set 00007h
MCR1_sa .set 00008h
MCR2_sa .set 00009h
RCERA_sa .set 0000Ah
RCERB_sa .set 0000Bh
XCERA_sa .set 0000Ch
XCERB_sa .set 0000Dh
PCR_sa .set 0000Eh
.if ($isdefed("_SD5410_"))
McDXR1 .set DXR1_0
IMASK .set (1 << 4)
SPSA .set SPSA0_a
SPAD .set SPAD0_a
.endif
.if ($isdefed("_DSK5402_"))
MCBSP0_TO_CODEC0 .set 0xFE
MCBSP1_TO_CODEC1 .set 0xFD
CODEC1_FC_ON .set 0x8
CODEC0_FC_ON .set 0x4
CPLD_CTRL2 .set 0x4
McDXR1 .set DXR1_1
IMASK .set (1 << 10)
SPSA .set SPSA1_a
SPAD .set SPAD1_a
.endif
WR_MCBSP_SUB_REG .macro addr,val
stm addr,SPSA
nop
stm val,SPAD
nop
.endm
RD_MCBSP_SUB_REG .macro addr,acc
stm #:addr:,SPSA
nop
ldm SPAD,acc
nop
nop
nop
.endm
;
; ======== WAITTRX ========
; This macro is used instead of WAITINR since we don't want
; to enable interrupts in DSS_init().
;
.if ($isdefed("_SD5410_"))
WAITTRX .macro
WAITX?
stm #SPCR2_sa, SPSA ; select McBSP0 SPCR2 register
ld SPAD, A ; read SPCR2
and #1<<1, A ; check XRDY bit
bc DONEX?, ANEQ
b WAITX?
nop
DONEX?
.endm
.endif
.if ($isdefed("_DSK5402_"))
WAITTRX .macro
WAITR?
RD_MCBSP_SUB_REG SPCR1_sa,A
and #1<<1, A
bc WAITR?, AEQ
.endm
.endif
;
; Serial Port Control Register 1 (SPCR1)
;
I_SPCR1 .set 0020h; initial McBSP0 SPCR1 setting
;15 DLB 0 -> 1 Digital Loop Back
;14 RJUST 0 -> 00 Right Just 0 10 Left Justify
;13 RJUST 0 -> 01 Right Just SE 11 Reserved
;12 CLKSTOP 0 -> 00 10 Start Nodly
;11 CLKSTOP 0 -> 01 11 Start w dly
;10 RESERVED 0 -> 0
; 9 RESERVED 0 -> 0
; 8 RESERVED 0 -> 0
; 7 DXENA 0 -> 0 No Extra Delay
; 6 ABIS 0 -> 0 DISABLED 1 ENABLED
; 5 RINTM 1 -> 00 XRDY & ABIS 10 New Frame Sync
; 4 RINTM 0 -> 01 EOB,EOF 11 Sync Err int
; 3 RSYNCERR 0 -> 1 = Receiver Sync Error
; 2 RFULL 0 -> 1 = Receiver SR not empty
; 1 RRDY 0 -> 1 = Receiver Ready
; 0 RRST 0 -> 0 = Reset 1 = Enabled
RRST_s .set 1b << 0 ; RRST_ = 1 : receiver enable
;
; Serial Port Control Register 2 (SPCR2)
;
I_SPCR2 .set 00201h; initial McBSP0 SPCR2 setting
;15 RSVD 0
;14 RSVD 0
;13 RSVD 0
;12 RSVD -- 0
;11 RSVD 0
;10 RSVD 0
; 9 FREE 1 -> 0 Free Running Emulator
; 8 SOFT -- 0 -> 0 Soft Emulator
; 7 FRST- 0 -> 0 Frame sync -> use AD55
; 6 GRST- 0 -> 0 Sample Generator -> use AD55
; 5 XINTM 0 -> 00 XRDY & ABIS 10 New Frame Sync
; 4 XINTM -- 0 -> 01 EOB,EOF 11 Sync Err int
; 3 XSYNCERR 0 -> 1 = Sync Error
; 2 XEMPTY 0 -> 1 = Transmit SR not empty
; 1 XRDY 0 -> 1 = Transmit Ready
; 0 XRST 1 -> 0 = Reset 1 = Enabled
XRST_s .set (1b<<0 | 1b << 9) ; XRST=1, FREE=1 : XMIT enable, FREE mode
;
; Receive Control Register 1 (RCR1)
;
I_RCR1 .set 00040h ; 1 Word Per Frame 16 bits per word
; [15] 0 RESERVED
; [14] 0 RFRLEN1 0 : 1 words in frame
; [13] 0 RFRLEN1 1 : 2 words in frame
; [12] 0 RFRLEN1 . :
; [11] 0 RFRLEN1 . :
; [10] 0 RFRLEN1 . :
; [9] 0 RFRLEN1 . :
; [8] 0 RFRLEN1 7 : 8 words in frame
; [7] 0 RWDLEN1 = 000b : 8 bit
; [6] 1 RWDLEN1 = 010b : 16 bit
; [5] 0 RWDLEN1 = 100b : 24 bit
; RWDLEN1 = 100b : 32 bit
; [4] 0 RESERVED
; [3] 0 RESERVED
; [2] 0 RESERVED
; [1] 0 RESERVED
; [0] 0 RESERVED
;
; Receive Control Register 2 (RCR2)
;
I_RCR2 .set 0000h ; initial McBSP0 RCR2 setting
; [15] RPHASE
; [14] 0 RFRLEN2 0 : 1 words in frame
; [13] 0 RFRLEN2 1 : 2 words in frame
; [12] 0 RFRLEN2 . :
; [11] 0 RFRLEN2 . :
; [10] 0 RFRLEN2 . :
; [9] 0 RFRLEN2 . :
; [8] 0 RFRLEN2 7 : 8 words in frame
; [7-5] RWDLEN2
; [4-3] RCOMPAND
; [2] RFIG = 0 : ignore frame syncs after first
; [1] RDATDLY = 00b : 0-bit data delay
; [0] RDATDLY = 00b : 0-bit data delay
;
; Transmit Control Register 1 (XCR1)
;
I_XCR1 .set 0040h ; initial McBSP0 XCR1 setting
; [15] RESERVED
; [14] 0 XFRLEN1 0 : 1 words in frame
; [13] 0 XFRLEN1 1 : 2 words in frame
; [12] 0 XFRLEN1 . :
; [11] 0 XFRLEN1 . :
; [10] 0 XFRLEN1 . :
; [9] 0 XFRLEN1 . :
; [8] 0 XFRLEN1 7 : 8 words in frame
; [14-8] XWDLEN1 = 7 : 8 words in frame
; [7-5] XWDLEN1 = 000b : 8 bit
; [7-5] XWDLEN1 = 010b : 16 bit
; [7-5] XWDLEN1 = 100b : 24 bit
; [7-5] XWDLEN1 = 100b : 32 bit
; [4] 0 RESERVED
; [3] 0 RESERVED
; [2] 0 RESERVED
; [1] 0 RESERVED
; [0] 0 RESERVED
;
; Transmit Control Register 2 (XCR2)
;
I_XCR2 .set 0000h ; initial McBSP0 XCR2 setting
; [15] xPHASE
; [14] 0 XFRLEN1 0 : 1 words in frame
; [13] 0 XFRLEN1 1 : 2 words in frame
; [12] 0 XFRLEN1 . :
; [11] 0 XFRLEN1 . :
; [10] 0 XFRLEN1 . :
; [9] 0 XFRLEN1 . :
; [8] 0 XFRLEN1 7 : 8 words in frame
; [7-5] xWDLEN2
; [4-3] xCOMPAND
; [2] xFIG = 0 : ignore frame syncs after first
; [1-0] xDATDLY = 00b : 0-bit data delay
;
; Pin Control Register (PCR)
;
I_PCR .set 000Ch ; initial McBSP0 XCR2 setting
; [15] RSVD = 0
; [14] RSVD = 0
; [13] XIOEN = 0 : NOT GPIO
; [12] RIOEN = 0 : NOT GPIO
; [11] FSXM = 0 : FSX pin 0 - input, 1 - output
; [10] FSRM = 0 : FSR pin 0 - input, 1 - output
; [9] CLKXM = 0 : CLKX pin 0 - input, 1 - output
; [8] CLKRM = 0 : CLKR pin 0 - input, 1 - output
; [7] RSVD = 0
; [6] CLKS_STAT 0
; [5] DX_STAT 0
; [4] DR_STAT 0
; [3] FSXP = 1 : FSX 0 - active high, 1 - active low
; [2] FSRP = 1 : FSR 0 - active high, 1 - active low
; [1] CLKXP = 0 : 0 - sample on REdge , 1 - FEdge
; [0] CLKRP = 0 : 0 - sample on FEdge , 1 - REdge
;*************************************************************************
;* PROGRAM AD55 REGISTER MACRO
;*************************************************************************
.if ($isdefed("_DSK5402_"))
PROGREG .macro progword
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