odd_fren.txt

一个3分频的VHDL程序,方便学习且仅供学习之用

发一个3分频的VHDL程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY Odd_Fren is
port(Clk : in std_logic;
    O   : out std_logic);
end Odd_Fren;

architecture bev of Odd_Fren is
signal O_r,O_d     : std_logic_vector(1 downto 0) := "00"; 
signal O_ro,O_do,O_x : std_logic := '0';
signal O_t       : std_logic := '0';
begin
P1 : PROCESS(Clk,O_r)       
begin
  if(Clk'event and Clk='1') then
    case O_r is
    when "01"   => O_ro <= '1';
              O_r <= O_r + 1;
    when "10"   => O_ro <= '0';
              O_r <= "00";                  
    when others => O_r <= O_r + 1;
              O_ro <= '0';
    end case;   
  end if;
end PROCESS;

P2 : PROCESS(Clk,O_d)       
begin
  if(Clk'event and Clk='0') then
    case O_d is
    when "01"   => O_do <= '1';
              O_d <= O_d + 1;
    when "10"   => O_d <= "00";
              O_do <= '1';
    when others => O_d <= O_d + 1;
              O_do <= '0'; 
    end case;   
  end if;
end PROCESS;

O_x <= O_ro xor O_do;

P3 : PROCESS(O_x)   
begin
  if(O_x'event and O_x='1') then
    O_t <= not O_t;
    O <= O_t;
  end if;
end PROCESS;
  
end bev;
-----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY tst_Odd_Fren is end;

architecture test of tst_Odd_Fren is
COMPONENT Odd_Fren is
  port(Clk : in std_logic;
      O   : out std_logic);
end COMPONENT;

signal Clk : std_logic;
signal O   : std_logic;
begin
U0 : Odd_Fren port map(Clk,O);

PROCESS 
begin
  Clk <= '0';
  wait for 50 ns;
  Clk <= '1';
  wait for 50 ns;
end PROCESS;

end test;