vhdl语言的uart串行接口芯片程序.txt

VHDL语言的UART串行接口芯片程序,仅供学习使用

--divide by 256 counter
SIGNAL div3:STD_LOGIC_VECTOR(2 DOWNTO 0)=”000”;
--Divide by 8 counter
SIGNAL clkdivl3:STD_LOGIC;
BEGIN
div_13：PROCESS(syselk)
BBGIN
  IF(sysclk’EVENT AND sysclk=’1’)THEN
    IF(div1="1100")THEN div1<="0000";
  ELSE div1<=divl+1;
  END IF;
  END IF;
END PROCSS （clkdivl3）
BEGIN
  IF(clkdivl3’VENT AND clkdivl3=’1’)THEN
    div2<=div2+l;
  END IF;
END PROCESS;
 clkdiv13<=div1(3);

div_pro:PROCESS(clkdiv13); 
BEGIN 
 IF(clkdiv13’EVENT AND clkdiv13=’1’)THEN
   div2<=div2=1;
END IF; 
END PROCESS;
BclkX8<=div2(CONV_INTEGER(sel))；--select baud rate

div_8：PROCESS(BclkX8)
BEGIN
IF(BclkX8'EVENT AND BcLkXS=’1’)THEN
    div3<=dlv3+1;
    END IF;
    END PROCESS;
    bclk<=div3(2);
    END rtl;
附录4  UART总体的VHDL语言描述清单
LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.aLL;
    USE IEEe.STD_LOGIC_UNSIGNED.aLL;

ENTITY UART IS
  PORT(
    reset, cs, R_W, clk, RxD, a1,a0:IN STD_LOGIC;
    d:INOUT STD_LOGiC_VECTOR(7 DOWNTO 0);
     IRQ, TxD:OUT STD_LOGIC);
END UART;

ARCHITECTURE rtl OF UART IS
COMPONENT UART_Receiver
     PORT(
      RxD,BclkX8,sysclk, reset, RDRF:IN STD_LOGIC;
       RDR:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    setRDRF, SETOE,setFE:OUT STD_LOGIC);
END COMPONENT;
COMPONENT UART_transmitter
  PORT(
     Bclk,sysclk,reset, TDRE, IoadTDR:IN STD_LOGIC;
     DBUS:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     setTDRE, TxD:OUT STD_LOGIC);
END COMPONENT;
COMPONENT UART_clkdiv
  PORT(
     Sysclk:IN STD_LOGIC;
     sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
     BclkX8:BUFFER STD_LOGIC;
     Bclk:OUT STD_LOGIC);
END COMPONENT;
SIGNAL RDR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SCSR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SCCR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL TDRE, RDRF, OE, FE, TIE, RIE:STD_LOGIC;
SIGNAL Baudsel :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr :STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL setTDRE, setRDRF, setOE, setFE, loadTDR, loadSCCR:STD_LOGIC;
SIGNAL clrRDRF,Bclk,BclkX8,SCI_Read, SCI_Write:STD_LOGIC;
BEGIN
addr<=a1&a0;
u0:UART_Receiver PORT MAP(RxD,BclkX8,clk,reset,RDRF,RDR,setRDRF,setOE,setFE);
U1:UART_Transmitter PORT MAP(Bclk,clk,reset,TDRE,LoadTDR,d,
          setTDRE,TxD);                         
u2:UART_clkdiv PORT MAP(clk,Baudsel,BclkX8,Bclk);
PROCESS(clk, reset)
BEGIN
  IF(reset='0') THEN
  TDRE<='1'; RDRF<='0'; oE<='0'; FE<='0';
  TIE<= '0'; RIE<='0';
ELSIF(clk'EVENT AND clk='1') THEN
TDRE<=(setRDRf AND NOT TDRE) OR (NOT loadTDR AND TDRE);
RDRF<=(setRDRF AND NOT RDRF) OR (NOT clrRDRF AND RDRF);
  OE<=(setOE AND NOT OE) OR (NOT clrRDRF AND OE);
  FE<=(setFE AND NOT FE) OR (NOT clrRDRF AND FE);
   IF(loadSCCR='1') THEN TIE<=d(7); RIE<=d(6);
                 Baudsel<=d(2 DOWNTO 0);
   END IF;
END IF;
END PROCESS;
IRQ<= '1' WHEN ((RIE='1' AND (RDRF='1' OR OE='1'))
                           OR(TIE='1'AND TDRE='1'))
 ELSE
       '0';
SCSR<= TDRE & RDRF & "0000" & OE & FE;
SCCR<=TIE & RIE & "000" & Baudsel;
SCI_Read <='1' WHEN (cs='1'AND R_W='1') ELSE
                '0';
SCI_Write<= '1' WHEN (cs='1' AND R_W='0') ELSE
                 '0';
clrRDRF <='1'  WHEN (SCI_Read='1' AND addr="00") ELSE
                '0';
loadTDR <='1' WHEN (SCI_Write='1' AND addr="00") ELSE 
                '0';
loadSCCR <='1' WHEN (SCI_Write='1' AND addr="10")ELSE
               '0';
d <="ZZZZZZZZ" WHEN (SCI_Read='0')ELSE
RDR        WHEN (addr="00")      ELSE
   SCSR        WHEN (addr="01")      ELSE
   SCCR;
END rtl;

LIRARY IEEE;
    USE IEEE.STD_LOGIC _1164．ALL;
    USE IESE .STD_LOGIC_UNSIGNED．ALL;

ENTITY UART IS
  PORT(
    reset, cs, R_W, clk, RxD, a1,a0:	IN STD_LOGIC;
    d:INOUT STD_LOG1C_ VECTOR(7 DOWNTO 0);
     IRQ, TxD:OUT STD_LOGIC);
END UART;

ARCHITECTURE rtl OF UART IS
COMPONENT UART_Receiver
     PORT(
      RxD,BclkX8,sysclk, reset, RDRF:IN STD_LOGIC;
       RDR:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    setRDRF, SETOE,setFE:OUT STD_LOGIC;
END COMPONENT;
COMPONENT UART_transmitter
  PORT(
     Bclk,sysclk,reset, TDRE, IoadTDR:IN STD_LOGIC;
     DBUS:IN STD_LOGIC_ VECTOR(7 DOWNTO 0);
     setTDRE, TxD:OUT STD_LOGIC);
END COMPONENT;
COMPONENT UART_clkdiv
  PORT(
     Sysclk:IN STD_LOGIC;
     sel:IN STD_LOGIC _VECTOR(2 DOWNTO 0);
     BclkX8:BUFFER STD_LOGIC;
     Bclk:OUT STD_LOGIC);
END COMPONENT;,
SIGNAL RDR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SCSR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SCCR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL TDRE, RDRF, OE, FE, TIE, RIE:STD_LOGIC;
SIGNAL Baudsel :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr :STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNALsetTDRE, setRDRF, setOE, setFE, loadTDR, loadSCCR:STD_LOGIC;
SIGNALclrRDRF,Bclk,BclkX8,SCI_Read, SCI_Write:STD_LOGIC;
BEGIN
addr<=a1&a0;
u0:UART_ReceiverPORT MAP(RxD,BclkX8,clk,reset,RDRF,RDR,setRDRF,setOE,setFE);
U1:UART_Transmitter PORT MAP(Bclk,clk,reset,TDRE,loadTDR,d,
          setTDRE,TxD);                         
u2:UART_clkdiv PORT MAP(clk,Baudsel,BclkX8,Bclk);
PROCESS(clk, reset)
BEGIN
  IF(reset='0') THEN
  TDRE<='1'; RDRF<='0'; 0E<='0'; FE<='0';
  TIE<= '0'; RIE<='0'
ELSIF(clk'EVENT AND clk='1') THEN
TDRE<=(setRDRE AND NOT TDRE) OR (NOT loadTDRE AND TDRE);
RDRF<=(setRDRF AND NOT RDRF) OR (NOT clrRDRF AND RDRF);
  OE<=(setOE AND NOT OE) OR (NOT clrRDRF AND OE);
  FE<=setFE AND NOT FE) OR (NOT clrRDRF AND FE);
   IF(loadSCCR=’1’) THEN TIE<=d(7); RIE<=d(6);
                 Baudsel<=d(2 DOWNTO 0);
   END IF;
END IF;
END PROCESS;
IRQ<= '1' WHEN ((RIE=' 1' AND (RDRF='1' OR OE=’1’));
                           OR(TIE='I'AND TDRE='1’))
 ELSE
       '0';
SCSR<= TDRE & RDRF & "0000" & OE & FE;
SCCR<=TIE & RIE & "000" & Baudsel;
SCI_Read <=' 1' WHEN (cs=’1’, AND R_W='1') ELSE
                '0';
SCI_Write<= '1' WHEN (cs=’1’ AND R_ W='0') ELSE
                 '0';
clrRDRF <= '1’  WHEN (SCI_Read=’1’ AND addr=”00”) ELSE
                ’0’;
loadTDR <= '1’ WHEN (SCI_Write=’1’ AND addr=”00”) ELSE 
                ’0’;
loadSCCR <=’1’ WHEN (SCI_Write=’1’ AND addr=”10”)ELSE
               ’0’;
d <=”ZZZZZZZZ” WHEN (SCI_Read=’0’)ELSE
RDR        WHEN (addr=-"00")      ELSE
   SCSR        WHEN (addr="0l')      ELSE
   SCCR;
END rtl;
LIbRARY IEEE;
    USE IEEE.STD_LOGIC_1164.aLL;
    USE IEEe.STD_LOGIC_UNSIGNED.aLL;

ENTITY UART IS
  PORT(
    reset, cs, R_W, clk, RxD, a1,a0:IN STD_LOGIC;
    d:INOUT STD_LOGiC_VECTOR(7 DOWNTO 0);
     IRQ, TxD:OUT STD_LOGIC);
END UART;

ARCHITECTURE rtl OF UART IS
COMPONENT UART_Receiver
     PORT(
      RxD,BclkX8,sysclk, reset, RDRF:IN STD_LOGIC;
       RDR:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    setRDRF, SETOE,setFE:OUT STD_LOGIC);
END COMPONENT;
COMPONENT UART_transmitter
  PORT(
     Bclk,sysclk,reset, TDRE, IoadTDR:IN STD_LOGIC;
     DBUS:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     setTDRE, TxD:OUT STD_LOGIC);
END COMPONENT;
COMPONENT UART_clkdiv
  PORT(
     Sysclk:IN STD_LOGIC;
     sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
     BclkX8:BUFFER STD_LOGIC;
     Bclk:OUT STD_LOGIC);
END COMPONENT;
SIGNAL RDR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SCSR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SCCR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL TDRE, RDRF, OE, FE, TIE, RIE:STD_LOGIC;
SIGNAL Baudsel :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr :STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL setTDRE, setRDRF, setOE, setFE, loadTDR, loadSCCR:STD_LOGIC;
SIGNAL clrRDRF,Bclk,BclkX8,SCI_Read, SCI_Write:STD_LOGIC;
BEGIN
addr<=a1&a0;
u0:UART_Receiver PORT MAP(RxD,BclkX8,clk,reset,RDRF,RDR,setRDRF,setOE,setFE);
U1:UART_Transmitter PORT MAP(Bclk,clk,reset,TDRE,LoadTDR,d,
          setTDRE,TxD);                         
u2:UART_clkdiv PORT MAP(clk,Baudsel,BclkX8,Bclk);
PROCESS(clk, reset)
BEGIN
  IF(reset='0') THEN
  TDRE<='1'; RDRF<='0'; oE<='0'; FE<='0';
  TIE<= '0'; RIE<='0';
ELSIF(clk'EVENT AND clk='1') THEN
TDRE<=(setRDRf AND NOT TDRE) OR (NOT loadTDR AND TDRE);
RDRF<=(setRDRF AND NOT RDRF) OR (NOT clrRDRF AND RDRF);
  OE<=(setOE AND NOT OE) OR (NOT clrRDRF AND OE);
  FE<=(setFE AND NOT FE) OR (NOT clrRDRF AND FE);
   IF(loadSCCR='1') THEN TIE<=d(7); RIE<=d(6);
                 Baudsel<=d(2 DOWNTO 0);
   END IF;
END IF;
END PROCESS;
IRQ<= '1' WHEN ((RIE='1' AND (RDRF='1' OR OE='1'))
                           OR(TIE='1'AND TDRE='1'))
 ELSE
       '0';
SCSR<= TDRE & RDRF & "0000" & OE & FE;
SCCR<=TIE & RIE & "000" & Baudsel;
SCI_Read <='1' WHEN (cs='1'AND R_W='1') ELSE
                '0';
SCI_Write<= '1' WHEN (cs='1' AND R_W='0') ELSE
                 '0';
clrRDRF <='1'  WHEN (SCI_Read='1' AND addr="00") ELSE
                '0';
loadTDR <='1' WHEN (SCI_Write='1' AND addr="00") ELSE 
                '0';
loadSCCR <='1' WHEN (SCI_Write='1' AND addr="10")ELSE
               '0';
d <="ZZZZZZZZ" WHEN (SCI_Read='0')ELSE
RDR        WHEN (addr="00")      ELSE
   SCSR        WHEN (addr="01")      ELSE
   SCCR;
END rtl;