vhdl语言的uart串行接口芯片程序.txt

VHDL语言的UART串行接口芯片程序,仅供学习使用

VHDL语言的UART串行接口芯片设计程序清单
附录1  数据接收据器的VHDL语言描述清单
LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_signed.all;

ENTITY UART_receiver IS
  PORT(RxD, Bclkx8, sysclk, reset, RDRF:IN STD_LOGIC;
       RDR:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       setRDRF, setOE, setFE:OUT STD_lOGIC);
END UART_receiver;

ARCHITECTURE rtl OF UART_receiver IS

TYPE stateTYPE IS (R_WAiT, START_DETECTED,R_DATA);
SIGNAL state, nextstate:stateTYPE;
SIGNAL RSR:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cnt1:INTEGER RANGE 0 TO 7;
SIGNAL cnt2:INTEGER RANGE 0 TO 8;
signal clr1,clr2 : std_logic;
SIGNAL inc1, inc2, shftRSR, loadRDR : STD_LOGIC;
SIGNAL Bclkx8_Dlayed, Bclkx8_rising:STD_LOGIC;

BEGIN
BclkX8_rising<=Bclkx8 AND (NOT Bclkx8_dlayed);
R_control:PROCESS(state,RxD,RDRF,cnt1,cnt2,BclkX8_rising)
BEGIN
  --inc1<='0';inc2<='0';
  --clr1<='0';clr2<='0';
shftRSR<='0'; loadRDR<='0'; setRDRF<='0'; setOE<='0'; 
setFE<='0';
CASE state IS
    WHEN R_WAIT =>
         IF(Rxd='0')THEN nextstate<=START_DETECTED;
            ELSE nextstate<=R_WAIT;
         END IF;
     WHEN START_DETECTED=>
            IF(Bclkx8_rising='0')THEN 
               nextstate<=START_DETECTED;
            ELSIF(RxD='1') THEN 
               clr1<='1';nextstate<=R_WAIT;
            ELSIF(cnt1=3)  THEN 
               clr1 <='1'; nextstate<=R_WAIT;
            ELSE 
               inc1<='1';nextstate<=START_DETECTED; 
            END IF;
WHEN R_DATA =>
    IF(Bclkx8_rising='0') THEN nextstate<=R_DATA;
ELSE inc1<='1';
  IF(cnt1 /= 7) THEN nextstate<=R_DATA;
  ELSIF(cnt2/=8) THEN
      shftRSR<='1'; inc2<='1'; clr1<='1';
     nextstate<=R_DATA;
  ELSE
     Nextstate<=R_WAIT;
     setRDRF<='1'; clr1<='1'; clr2<='1';
     IF(RDRF='1') THEN setOE<='1';
     ELSIF(RXD='0') THEN setFE<='1';
     ELSE loadRDR<='1';
     END IF;
                  END IF;
            END IF;
     END CASE;
END PROCESS;
R_update:PROCESS(sysclk,reset)
BEGIN
 IF(reset='0') THEN state<=R_WAIT;BclkX8_Dlayed<='0';
     cnt1<=0; cnt2<=0;
 ELSIF(syscLk'EVENT AND sysclk='1') THEN
    state<=nextstate;
    IF(clr1='1') THEN cnt1 <=0;
     ELSIF(inc1='1') THEN cnt1<=cnt1+1;
    END IF;
    IF(clr2='1') THEN cnt2<=0;
     ELSIF(inc2='1') THEN cnt2<=cnt2+1;
    END IF;
    IF(shftRSR='1') THEN RSR<= RxD & RsR(7 DOWNTO 1);
    END IF;
    IF(loadRDR='1') THEN RDR<=RSR;
   END IF;
   BclkX8_Dlayed<=BclkX8;
END IF;
 END PROCESS;
 END rtl;

附录2  数据发送器的VHDL语言描述清单
ng<=Bclk And (not Bclk_Dlayed);
TLIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.aLL;

ENTITY UART_transmitter is 
  PORT(Bclk,sysclk,reset,TDRE,LoadTDR:in STD_LOGIC;
  DBUS: in STD_LOGIC_VECTOR(7 DOWNTO 0);
  setTDRE,TxD:oUT STD_LOGIC);
END UART_transmitter;

ARCHITECTURE rt1 OF UART_transmitter IS
TYPE stateTYPE IS(T_WAIT,SYNCH,T_DATA);
SIGNAL state,nextstate:stateTYPE;
SIGNAL TDR:sTD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL TSR:sTD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNAL Bcnt:iNTEGER RANGE 0 TO 9;
SIGNAL inc,clr,loadTSR,shftTSR,start:STD_LOGIC;
SIGNAL Bclk_rising,Bclk_Dlayed:sTD_LOGIC;
BEGIN
TxD<=TSR(0);    
setTDRE<=loadTSR;
Bclk_risi_control:PROCESS(state,TDRE,Bcnt,Bclk_rising)
BEGIN
inc<='0';clr<='0';loadTSR<='0';shftTSR<='0';
start<='0';    
CASE state IS
    WHEN T_WAIT=>
 IF(TDRE='0')THEN loadTSR<='1';nextstate<=SYNCH;
ELSE nextstate<=T_WAIT;
    END IF;
    WHEN SYNCH=>
IF(Bclk_rising='1')THEN start<='1';nextstate<=T_DATA;
    ELSE nextState<=SYNCH;
    END IF;
    WHEN T_DATA=>
    IF(Bclk_rising='0')THEN nextstate<=T_DATA;
    ELSIF(Bcnt/=9)THEN
       shftTSR<='1';inc<='1';nextstate<=T_DATA;
    ELSE clr<='1';nextstate<=T_WAIT;
    END IF;
  END CASE;
END PROCESS T_control;

T_update:PROCESS(sysclk,reset)
BEGIN
IF(reset='0')THEN
   TSR<="111111111";state<=T_WAIT;Bcnt<=0;Bclk_dlayed<='0';
ELSIF(sysclk'EVENT AND sysclk='1')THEN
    State<=nextstate;
   IF(clr='1')THEN Bcnt<=0;ELSIF(inc= '1')THEN
                  Bcnt<=Bcnt+1;
   END IF;
  IF(loadTDR='1')THEN TDR<=DBUS;END IF;
  IF(loadTSR='1')THEN TSR<=TDR&'1';
  ELSIF(START='1')THEN TSR(0)<='0';
  ELSIF(shftTSR='1')THEN TSR<='1'&TSR(8 DOWNTO 1);
  END IF;
Bclk_Dlayed<=Bclk;
  END IF; 
 IF(loadTDR='1')THEN TDR<=DBUS;END IF;
IF(loadTSR='1')THEn TSR<=TDR&'1';
ELSE IF(START='1')THEN TSR(0)<='0';
ELSE IF(shftTSR='1')THEN TSR<='1'&TSR(8 DOWNTO 1); 
END IF;
Bclk_Dlayed<=Bclk;


End If;end if;
end process T_update;

End rt1;

LIBRARY IEEE;
USE IEEE．STD_LOGIC_1164．ALL;

ENTITY UART_transmitter IS
  PORT(
  Bclk，sysclk，reset，TDRE，loadTDR：IN STD_LOGIC;
  DBUS：INSTD_LOGIC_VECTOR(7 DOWNTO 0);
  setTDRE，TxD：OUT STD_ LOGIC);
END UART_transmitter;

ARCHITECTURE rtl OF UART_transmitter IS
TYPEstateTYPE IS(T_WAlT，SYNCH，T—DATA);
SIGNAL state，nextstate：stateTYPE；
SIGNAL TDR：STD_LOGIC__VECTOR(7 DOWNTO 0)：
SIGNAL TSR：STD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNALBcnt：INTEGER RANGE 0 TO 9;
SIGNAL inc，clr，loadTSR，shftTSR，start：STD-LOGIC;
SIGNAL Bclk_rising，Bclk_Dlayed：STD_LOGIC;
BEGIN
TxD<=TSR(0)：    
setTDRE<=loadTSR；
Bclk_rising<=Bclk AND (N0T Bclk_Dlayed);

T_control:PROCESS(state，TDRE，Bcnt，Bclk_rising)
BEGIN
inc=’0’：clr<='0'；loadTSR<=’0’；shftTSR<='0';
start<='0';    
CASE state IS
    WHEN T_WAIT=>
 IF(TDRE=’0’)THEN loadTSR<=’1’nextstate<=SYNCH;
ELSE nextstate<=T_WAIT;
    END lF;
    WHEN SYNCH=>
IF(Bclk_rising=’1’)THEN start<=’1’;nextstate<=T_DATA;
    ELSE nextState<=SYNCH;
    END IF;
    WHENT_ DATA=>
    IF(Bclk_rising='0')THEN nextstate<=T_DATA;
    ELSIF(Bcnt／=9)THEN
       shftTSR='l';iucl;nextstate<=T_DATA;
    ELSE clr<=’1’;nextstate<=T_WAIT;
    END IF;
  END CASE;
END PROCESS;

T_updale;PROCESS(sysclk,reset)
BEGIN
IF(reset=’0’)THEN
   TSR<=”111111111”;state<=T_WAIT,Bcnt<=0;Bclk_dlayed<=’0’;
ELSIF(sysclk’EVENT AND sysclk=’1’)THEN
    State<=nextstate;
IF(clr=’l’)THEN Bcnt<=0;ELSIF(inc=’l')THEN
                  Bcnt<=Bcnt+1;
  END IF;
  IF（loadTDR=T)THENTDR<=DBUS;ENDIF;
 IF(loadTSR=‘1’)THEN TSR<=TDR&’1’;
ELSIF(START='I')THENTSR(0)<=‘0’;
ELSIF(shffrSR='1')THENTSR<='I，&TSR(8DOWNT01);ENDIF;
Bclk_Dlayed<=Bclk;
  END IF; 
IF(loadTDR=’1’)THEN TDR<=DBUS;END IF;
IF(loadTSR=’1’)THER TSR<=TDR&’1’;
ELSEIF(START=’1’)THEN TSR(0),=’0’;
ELSEIF(shiftTSR=’1’)THEN TSR<=’1’&TSR(8 DOWNTO 1); 
END IF;
Bclk_Dlayed<=Bclk;

END IF;
END PROCESS;
END rtl;

附录3  波特率发生器的VHDL语言描述清单
LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGlC_UNSIGNED.ALL;

ENTITY UART_clkdiv IS
  POPT(
    sysclk:iN STD_LOGlC;
    sel:IN STD_LOGIC_VECTOR (2 DOWNTO 0);
    BclkX8:BUFFER STD_LOGIC;
    Bclk:OUT STD_LOGIC);
END UART_clkdiv; 

ARCHITECTURE rtl OF UART_clkdiv IS
SIGNAL divl:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL div2:STD_LOGIC_VECTOR (7 DOWNTO 0):="00000000";
SIGNAL div3:STD_LOGIC_VECTOR(2 DOWNTO 0)="000";
SIGNAL clkdivl3:STD_LOGIC;
BEGIN
div_13:prOCESS(syselk)
BBGIN
  IF(sysclk'EVENT AND sysclk='1')THEN
    IF(div1="1100")THEN div1<="0000";
  ELSE div1<=divl+1;
  END IF;
  END IF;
END PROCeSS;
BEGIN
  IF(clkdivl3'VENT AND clkdivl3='1')THEN
    div2<=div2+l;
  END IF;
END PROCESS;
 clkdiv13<=div1(3);

div_pro:PROCESS(clkdiv13); 
BEGIN 
 IF(clkdiv13'EVENT AND clkdiv13='1')THEN
   div2<=div2=1;
END IF; 
END PROCESS;
BclkX8<=div2(CONV_INTEGER(sel))；--select baud rate

div_8:pROCESS(BclkX8)
BEGIN
IF(BclkX8'EVENT AND BcLkXS='1')THEN
    div3<=dlv3+1;
    END IF;
    END PROCESS;
    bclk<=div3(2);
    END rtl;
 LIBRARY  IEEE;
    USE IEEE.STD_LOGIC_11164.ALL;
    USE IEEE.STD_LOGlC_UNSIGNED.ALL;

ENTITY UART_clkdiv IS
  POPT(
    sysclk：IN STD_LOGlC;
    sel:IN STD_LOGIC_VECTOR (2 DOWNTO 0);
    BclkX8：BUFFER STD_LOGIC;
    Bclk:OUT STD_LOGIC);
END UART_clkdiv; 

ARCHITECTURE rtl OF UART_clkdiv IS
SIGNAL divl:STD_LOGIC_VECTOR(3 DOWNTO 0)：=”0000”;
--divide by 13  counter
SIGNAL div2：STD_LOGIC_VECTOR (7 DOWNTO 0)：=”00000000”;