we.v

采用Verilog语言,实现了FPGA控制视频芯片的数据采集,并将数据按帧存储起来

/*产生写FIFO信号,在默认情况下，一帧数据是640*480大小，并且分两场传输，奇场和偶场*/
module we(reset,pclk,hsync,vsync,wrst,wclk,we_s,int1r,yi,uvi,yo,uvo,GPIO3,rrst);
input  reset,pclk,hsync,vsync,GPIO3,rrst;
input[7:0] yi,uvi; 

output wrst,wclk,we_s,int1r;
output[7:0] yo,uvo;

parameter hs=150,
          he=462,
          vs=5,
          ve=214,
          int1const=10;
reg      wrst,we_s,int1,start,framebegin,int1r;
reg[7:0] yo,uvo;
reg[3:0] int1c;
reg[10:0] h_counter;
reg[10:0] v_counter;
reg[20:0]p_counter;
assign wclk=pclk;   

always@(GPIO3)  
begin
if(GPIO3==0)            //the request is from DSP to notifying the FPGA writing data into FIFO        
begin         //data are written to the FIFO ,using fpga_clk
start=0;
end
else 
begin
start=1;
end
end

always@( posedge hsync or negedge reset)
begin
 if (reset==0)
   v_counter=vs;
 else if(rrst==1)
  begin
   v_counter=vs;
  end
 else if(framebegin==1)
  begin
  if(v_counter<ve)
    v_counter=v_counter+1;
  else
    v_counter=ve;
  end
end

/*always@(posedge vsync or posedge hsync or negedge reset)
begin
 if (reset==0)
   v_counter=0;
 else if(vsync==1)
  begin
   if(readfinish==1)
   begin
   v_counter=0;
   end
   else 
   v_counter=v_const;
  end
 else 
  begin
  if(v_counter<v_const)
    v_counter=v_counter+1;
  else
    v_counter=v_const;
  end
end
*/

always @(posedge pclk or negedge reset)   /*DSP的复位信号给CMOS复位的同时也会初始化FPGA的寄存器*/
 begin 
  if(reset==0)
       begin
       h_counter=hs;
       we_s=1;
       wrst=0;
       int1r=1;
       yo=0;
       uvo=0;
       framebegin=0;
       wait (reset!=0);
       end
 else  if(start==1)                //DSP program begin and  give the command to acquire data
   begin
      if (vsync)         /*场同步信号到来*/
           begin
          //   int1r=1;
             wrst=0;
             h_counter=hs;
             yo=0;
             uvo=0;
             framebegin=1;
           end
       else if(framebegin==1)   //保证完整的一帧数据写入
         begin
          if(!hsync)      /*行回扫信号或者场与行之间的间隙*/
           begin 
             h_counter=hs;
             //wrst=1;
             we_s=1;
             yo=0;
             uvo=0;
           end
          else                      /*行同步信号到来 */
           begin
            if(v_counter<ve) 
             begin
              if(h_counter<he) 
               begin
                 we_s=0;
                 wrst=1;
                 h_counter=h_counter+1; /*行内象素个数记数，记到h_const个*/
                 yo= uvi;
                 uvo=yi;
               end
              else        /*一行数据写完*/
               begin
                 we_s=1;
                 wrst=1;
                 h_counter=he;
                 yo=0;
                 uvo=0;
               end
             end
            else  
              begin   /*一场数据(240行)写完，产生中断*/
                we_s=1;
                int1r=0;
                h_counter=he;
                yo=0;
                uvo=0;
                framebegin=0;
              end
           end
         end
     else          //丢弃当前帧，直到新的一帧重新开始 framebegin==0
        begin
      //  int1r=1;
        wrst=0;
        we_s=1;
        h_counter=hs;
        yo=0;
        uvo=0;
        framebegin=0;
        end
   end
 else              //start==0
  begin
   we_s=1;
   int1r=1;
   yo=0;
   uvo=0;
   wrst=0;
   framebegin=0;
  end
end

/*always@(negedge int1r or posedge pclk)
begin
if(int1r==0)
begin
int1=0;
int1c=0;
end
else
if(int1c<int1const)
begin
int1=0;
int1c=int1c+1;
end
else
begin
int1=1;
int1c=int1const;
end
end
*/  
endmodule