mux16_1.map.rpt

本程序实现了对输入数路的16选1功能

+---------------------------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |mux16_1                   ; 12 (12)     ; 0            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 73   ; 0            ; 12 (12)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |mux16_1            ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 16:1               ; 4 bits    ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; No         ; |mux16_1|mout~3            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |mux16_1 ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type                                           ;
+----------------+-------+------------------------------------------------+
; width          ; 4     ; Integer                                        ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: sel4m1:u1 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; width          ; 4     ; Integer                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: sel4m1:u2 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; width          ; 4     ; Integer                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: sel4m1:u3 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; width          ; 4     ; Integer                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: sel4m1:u4 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; width          ; 4     ; Integer                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Dec 20 16:54:54 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mux16_1 -c mux16_1
Info: Found 2 design units, including 2 entities, in source file mux16_1.v
    Info: Found entity 1: mux16_1
    Info: Found entity 2: sel4m1
Info: Elaborating entity "mux16_1" for the top level hierarchy
Warning (10235): Verilog HDL Always Construct warning at mux16_1.v(19): variable "mout1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at mux16_1.v(20): variable "mout2" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at mux16_1.v(21): variable "mout3" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at mux16_1.v(22): variable "mout4" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info: Elaborating entity "sel4m1" for hierarchy "sel4m1:u1"
Warning: Design contains 50 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "sel[2]"
    Warning: No output dependent on input pin "sel[3]"
    Warning: No output dependent on input pin "in3[0]"
    Warning: No output dependent on input pin "in2[0]"
    Warning: No output dependent on input pin "in4[0]"
    Warning: No output dependent on input pin "in9[0]"
    Warning: No output dependent on input pin "in10[0]"
    Warning: No output dependent on input pin "in12[0]"
    Warning: No output dependent on input pin "in5[0]"
    Warning: No output dependent on input pin "in7[0]"
    Warning: No output dependent on input pin "in8[0]"
    Warning: No output dependent on input pin "in13[0]"
    Warning: No output dependent on input pin "in15[0]"
    Warning: No output dependent on input pin "in14[0]"
    Warning: No output dependent on input pin "in3[1]"
    Warning: No output dependent on input pin "in2[1]"
    Warning: No output dependent on input pin "in4[1]"
    Warning: No output dependent on input pin "in9[1]"
    Warning: No output dependent on input pin "in10[1]"
    Warning: No output dependent on input pin "in12[1]"
    Warning: No output dependent on input pin "in5[1]"
    Warning: No output dependent on input pin "in7[1]"
    Warning: No output dependent on input pin "in8[1]"
    Warning: No output dependent on input pin "in13[1]"
    Warning: No output dependent on input pin "in15[1]"
    Warning: No output dependent on input pin "in14[1]"
    Warning: No output dependent on input pin "in3[2]"
    Warning: No output dependent on input pin "in2[2]"
    Warning: No output dependent on input pin "in4[2]"
    Warning: No output dependent on input pin "in9[2]"
    Warning: No output dependent on input pin "in10[2]"
    Warning: No output dependent on input pin "in12[2]"
    Warning: No output dependent on input pin "in5[2]"
    Warning: No output dependent on input pin "in7[2]"
    Warning: No output dependent on input pin "in8[2]"
    Warning: No output dependent on input pin "in13[2]"
    Warning: No output dependent on input pin "in15[2]"
    Warning: No output dependent on input pin "in14[2]"
    Warning: No output dependent on input pin "in3[3]"
    Warning: No output dependent on input pin "in2[3]"
    Warning: No output dependent on input pin "in4[3]"
    Warning: No output dependent on input pin "in9[3]"
    Warning: No output dependent on input pin "in10[3]"
    Warning: No output dependent on input pin "in12[3]"
    Warning: No output dependent on input pin "in5[3]"
    Warning: No output dependent on input pin "in7[3]"
    Warning: No output dependent on input pin "in8[3]"
    Warning: No output dependent on input pin "in13[3]"
    Warning: No output dependent on input pin "in15[3]"
    Warning: No output dependent on input pin "in14[3]"
Info: Implemented 85 device resources after synthesis - the final resource count might be different
    Info: Implemented 69 input pins
    Info: Implemented 4 output pins
    Info: Implemented 12 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 55 warnings
    Info: Processing ended: Wed Dec 20 16:54:58 2006
    Info: Elapsed time: 00:00:05