📄 mux16_1.sim.rpt
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; |mux16_1|Selector3~8 ; |mux16_1|Selector3~8 ; out0 ;
; |mux16_1|Selector3~9 ; |mux16_1|Selector3~9 ; out0 ;
; |mux16_1|sel4m1:u4|Selector0~6 ; |mux16_1|sel4m1:u4|Selector0~6 ; out0 ;
; |mux16_1|sel4m1:u4|Selector0~7 ; |mux16_1|sel4m1:u4|Selector0~7 ; out0 ;
; |mux16_1|sel4m1:u4|Selector0~8 ; |mux16_1|sel4m1:u4|Selector0~8 ; out0 ;
; |mux16_1|sel4m1:u4|Selector1~5 ; |mux16_1|sel4m1:u4|Selector1~5 ; out0 ;
; |mux16_1|sel4m1:u4|Selector1~6 ; |mux16_1|sel4m1:u4|Selector1~6 ; out0 ;
; |mux16_1|sel4m1:u4|Selector1~7 ; |mux16_1|sel4m1:u4|Selector1~7 ; out0 ;
; |mux16_1|sel4m1:u4|Selector1~8 ; |mux16_1|sel4m1:u4|Selector1~8 ; out0 ;
; |mux16_1|sel4m1:u4|Selector1~9 ; |mux16_1|sel4m1:u4|Selector1~9 ; out0 ;
; |mux16_1|sel4m1:u4|Selector2~6 ; |mux16_1|sel4m1:u4|Selector2~6 ; out0 ;
; |mux16_1|sel4m1:u4|Selector2~7 ; |mux16_1|sel4m1:u4|Selector2~7 ; out0 ;
; |mux16_1|sel4m1:u4|Selector2~8 ; |mux16_1|sel4m1:u4|Selector2~8 ; out0 ;
; |mux16_1|sel4m1:u4|Selector3~5 ; |mux16_1|sel4m1:u4|Selector3~5 ; out0 ;
; |mux16_1|sel4m1:u4|Selector3~6 ; |mux16_1|sel4m1:u4|Selector3~6 ; out0 ;
; |mux16_1|sel4m1:u4|Selector3~7 ; |mux16_1|sel4m1:u4|Selector3~7 ; out0 ;
; |mux16_1|sel4m1:u4|Selector3~8 ; |mux16_1|sel4m1:u4|Selector3~8 ; out0 ;
; |mux16_1|sel4m1:u4|Selector3~9 ; |mux16_1|sel4m1:u4|Selector3~9 ; out0 ;
; |mux16_1|sel4m1:u3|Selector0~6 ; |mux16_1|sel4m1:u3|Selector0~6 ; out0 ;
; |mux16_1|sel4m1:u3|Selector0~8 ; |mux16_1|sel4m1:u3|Selector0~8 ; out0 ;
; |mux16_1|sel4m1:u3|Selector0~9 ; |mux16_1|sel4m1:u3|Selector0~9 ; out0 ;
; |mux16_1|sel4m1:u3|Selector1~6 ; |mux16_1|sel4m1:u3|Selector1~6 ; out0 ;
; |mux16_1|sel4m1:u3|Selector1~8 ; |mux16_1|sel4m1:u3|Selector1~8 ; out0 ;
; |mux16_1|sel4m1:u3|Selector1~9 ; |mux16_1|sel4m1:u3|Selector1~9 ; out0 ;
; |mux16_1|sel4m1:u3|Selector2~6 ; |mux16_1|sel4m1:u3|Selector2~6 ; out0 ;
; |mux16_1|sel4m1:u3|Selector2~8 ; |mux16_1|sel4m1:u3|Selector2~8 ; out0 ;
; |mux16_1|sel4m1:u3|Selector3~6 ; |mux16_1|sel4m1:u3|Selector3~6 ; out0 ;
; |mux16_1|sel4m1:u3|Selector3~8 ; |mux16_1|sel4m1:u3|Selector3~8 ; out0 ;
; |mux16_1|sel4m1:u2|Selector0~6 ; |mux16_1|sel4m1:u2|Selector0~6 ; out0 ;
; |mux16_1|sel4m1:u2|Selector0~8 ; |mux16_1|sel4m1:u2|Selector0~8 ; out0 ;
; |mux16_1|sel4m1:u2|Selector0~9 ; |mux16_1|sel4m1:u2|Selector0~9 ; out0 ;
; |mux16_1|sel4m1:u2|Selector1~6 ; |mux16_1|sel4m1:u2|Selector1~6 ; out0 ;
; |mux16_1|sel4m1:u2|Selector1~8 ; |mux16_1|sel4m1:u2|Selector1~8 ; out0 ;
; |mux16_1|sel4m1:u2|Selector2~6 ; |mux16_1|sel4m1:u2|Selector2~6 ; out0 ;
; |mux16_1|sel4m1:u2|Selector2~8 ; |mux16_1|sel4m1:u2|Selector2~8 ; out0 ;
; |mux16_1|sel4m1:u2|Selector3~6 ; |mux16_1|sel4m1:u2|Selector3~6 ; out0 ;
; |mux16_1|sel4m1:u2|Selector3~8 ; |mux16_1|sel4m1:u2|Selector3~8 ; out0 ;
; |mux16_1|sel4m1:u1|Selector0~6 ; |mux16_1|sel4m1:u1|Selector0~6 ; out0 ;
; |mux16_1|sel4m1:u1|Selector0~8 ; |mux16_1|sel4m1:u1|Selector0~8 ; out0 ;
; |mux16_1|sel4m1:u1|Selector1~6 ; |mux16_1|sel4m1:u1|Selector1~6 ; out0 ;
; |mux16_1|sel4m1:u1|Selector1~8 ; |mux16_1|sel4m1:u1|Selector1~8 ; out0 ;
; |mux16_1|sel4m1:u1|Selector1~9 ; |mux16_1|sel4m1:u1|Selector1~9 ; out0 ;
; |mux16_1|sel4m1:u1|Selector2~7 ; |mux16_1|sel4m1:u1|Selector2~7 ; out0 ;
; |mux16_1|sel4m1:u1|Selector2~8 ; |mux16_1|sel4m1:u1|Selector2~8 ; out0 ;
; |mux16_1|sel4m1:u1|Selector3~6 ; |mux16_1|sel4m1:u1|Selector3~6 ; out0 ;
; |mux16_1|sel4m1:u1|Selector3~8 ; |mux16_1|sel4m1:u1|Selector3~8 ; out0 ;
; |mux16_1|Decoder0~6 ; |mux16_1|Decoder0~6 ; out0 ;
; |mux16_1|sel4m1:u4|Decoder0~6 ; |mux16_1|sel4m1:u4|Decoder0~6 ; out0 ;
; |mux16_1|sel4m1:u3|Decoder0~6 ; |mux16_1|sel4m1:u3|Decoder0~6 ; out0 ;
; |mux16_1|sel4m1:u2|Decoder0~6 ; |mux16_1|sel4m1:u2|Decoder0~6 ; out0 ;
; |mux16_1|sel4m1:u1|Decoder0~6 ; |mux16_1|sel4m1:u1|Decoder0~6 ; out0 ;
+--------------------------------+--------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+--------------------------------+--------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------------+--------------------------------+------------------+
; |mux16_1|in3[0] ; |mux16_1|in3[0] ; out ;
; |mux16_1|in4[2] ; |mux16_1|in4[2] ; out ;
; |mux16_1|in14[0] ; |mux16_1|in14[0] ; out ;
; |mux16_1|in14[1] ; |mux16_1|in14[1] ; out ;
; |mux16_1|in14[2] ; |mux16_1|in14[2] ; out ;
; |mux16_1|in14[3] ; |mux16_1|in14[3] ; out ;
; |mux16_1|in16[0] ; |mux16_1|in16[0] ; out ;
; |mux16_1|Selector0~6 ; |mux16_1|Selector0~6 ; out0 ;
; |mux16_1|Selector0~8 ; |mux16_1|Selector0~8 ; out0 ;
; |mux16_1|Selector1~6 ; |mux16_1|Selector1~6 ; out0 ;
; |mux16_1|Selector1~8 ; |mux16_1|Selector1~8 ; out0 ;
; |mux16_1|Selector2~6 ; |mux16_1|Selector2~6 ; out0 ;
; |mux16_1|Selector2~8 ; |mux16_1|Selector2~8 ; out0 ;
; |mux16_1|Selector3~6 ; |mux16_1|Selector3~6 ; out0 ;
; |mux16_1|Selector3~8 ; |mux16_1|Selector3~8 ; out0 ;
; |mux16_1|sel4m1:u4|Selector0~6 ; |mux16_1|sel4m1:u4|Selector0~6 ; out0 ;
; |mux16_1|sel4m1:u4|Selector1~6 ; |mux16_1|sel4m1:u4|Selector1~6 ; out0 ;
; |mux16_1|sel4m1:u4|Selector1~8 ; |mux16_1|sel4m1:u4|Selector1~8 ; out0 ;
; |mux16_1|sel4m1:u4|Selector1~9 ; |mux16_1|sel4m1:u4|Selector1~9 ; out0 ;
; |mux16_1|sel4m1:u4|Selector2~6 ; |mux16_1|sel4m1:u4|Selector2~6 ; out0 ;
; |mux16_1|sel4m1:u4|Selector2~8 ; |mux16_1|sel4m1:u4|Selector2~8 ; out0 ;
; |mux16_1|sel4m1:u4|Selector3~6 ; |mux16_1|sel4m1:u4|Selector3~6 ; out0 ;
; |mux16_1|sel4m1:u4|Selector3~9 ; |mux16_1|sel4m1:u4|Selector3~9 ; out0 ;
; |mux16_1|sel4m1:u3|Selector0~6 ; |mux16_1|sel4m1:u3|Selector0~6 ; out0 ;
; |mux16_1|sel4m1:u3|Selector0~8 ; |mux16_1|sel4m1:u3|Selector0~8 ; out0 ;
; |mux16_1|sel4m1:u3|Selector0~9 ; |mux16_1|sel4m1:u3|Selector0~9 ; out0 ;
; |mux16_1|sel4m1:u3|Selector1~6 ; |mux16_1|sel4m1:u3|Selector1~6 ; out0 ;
; |mux16_1|sel4m1:u3|Selector1~8 ; |mux16_1|sel4m1:u3|Selector1~8 ; out0 ;
; |mux16_1|sel4m1:u3|Selector1~9 ; |mux16_1|sel4m1:u3|Selector1~9 ; out0 ;
; |mux16_1|sel4m1:u3|Selector2~6 ; |mux16_1|sel4m1:u3|Selector2~6 ; out0 ;
; |mux16_1|sel4m1:u3|Selector2~8 ; |mux16_1|sel4m1:u3|Selector2~8 ; out0 ;
; |mux16_1|sel4m1:u3|Selector3~6 ; |mux16_1|sel4m1:u3|Selector3~6 ; out0 ;
; |mux16_1|sel4m1:u2|Selector0~6 ; |mux16_1|sel4m1:u2|Selector0~6 ; out0 ;
; |mux16_1|sel4m1:u2|Selector0~9 ; |mux16_1|sel4m1:u2|Selector0~9 ; out0 ;
; |mux16_1|sel4m1:u2|Selector1~6 ; |mux16_1|sel4m1:u2|Selector1~6 ; out0 ;
; |mux16_1|sel4m1:u2|Selector2~6 ; |mux16_1|sel4m1:u2|Selector2~6 ; out0 ;
; |mux16_1|sel4m1:u2|Selector3~6 ; |mux16_1|sel4m1:u2|Selector3~6 ; out0 ;
; |mux16_1|sel4m1:u1|Selector0~6 ; |mux16_1|sel4m1:u1|Selector0~6 ; out0 ;
; |mux16_1|sel4m1:u1|Selector1~6 ; |mux16_1|sel4m1:u1|Selector1~6 ; out0 ;
; |mux16_1|sel4m1:u1|Selector1~8 ; |mux16_1|sel4m1:u1|Selector1~8 ; out0 ;
; |mux16_1|sel4m1:u1|Selector1~9 ; |mux16_1|sel4m1:u1|Selector1~9 ; out0 ;
; |mux16_1|sel4m1:u1|Selector2~7 ; |mux16_1|sel4m1:u1|Selector2~7 ; out0 ;
; |mux16_1|sel4m1:u1|Selector3~6 ; |mux16_1|sel4m1:u1|Selector3~6 ; out0 ;
; |mux16_1|sel4m1:u1|Selector3~8 ; |mux16_1|sel4m1:u1|Selector3~8 ; out0 ;
+--------------------------------+--------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sat Dec 30 12:39:52 2006
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off mux16_1 -c mux16_1
Warning: Can't find signal in vector source file for input pin "|mux16_1|in14[0]"
Warning: Can't find signal in vector source file for input pin "|mux16_1|in14[1]"
Warning: Can't find signal in vector source file for input pin "|mux16_1|in14[2]"
Warning: Can't find signal in vector source file for input pin "|mux16_1|in14[3]"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 61.14 %
Info: Number of transitions in simulation is 463
Info: Vector file mux16_1.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 4 warnings
Info: Processing ended: Sat Dec 30 12:39:52 2006
Info: Elapsed time: 00:00:01
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