mux16_1.map.qmsg

本程序实现了对输入数路的16选1功能

{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "mout3 mux16_1.v(21) " "Warning (10235): Verilog HDL Always Construct warning at mux16_1.v(21): variable \"mout3\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 21 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "mout4 mux16_1.v(22) " "Warning (10235): Verilog HDL Always Construct warning at mux16_1.v(22): variable \"mout4\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 22 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sel4m1 sel4m1:u1 " "Info: Elaborating entity \"sel4m1\" for hierarchy \"sel4m1:u1\"" {  } { { "mux16_1.v" "u1" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 11 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "50 " "Warning: Design contains 50 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "sel\[2\] " "Warning: No output dependent on input pin \"sel\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "sel\[3\] " "Warning: No output dependent on input pin \"sel\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in3\[0\] " "Warning: No output dependent on input pin \"in3\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in2\[0\] " "Warning: No output dependent on input pin \"in2\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in4\[0\] " "Warning: No output dependent on input pin \"in4\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in9\[0\] " "Warning: No output dependent on input pin \"in9\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in10\[0\] " "Warning: No output dependent on input pin \"in10\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in12\[0\] " "Warning: No output dependent on input pin \"in12\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in5\[0\] " "Warning: No output dependent on input pin \"in5\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in7\[0\] " "Warning: No output dependent on input pin \"in7\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in8\[0\] " "Warning: No output dependent on input pin \"in8\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in13\[0\] " "Warning: No output dependent on input pin \"in13\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in15\[0\] " "Warning: No output dependent on input pin \"in15\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in14\[0\] " "Warning: No output dependent on input pin \"in14\[0\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in3\[1\] " "Warning: No output dependent on input pin \"in3\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in2\[1\] " "Warning: No output dependent on input pin \"in2\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in4\[1\] " "Warning: No output dependent on input pin \"in4\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in9\[1\] " "Warning: No output dependent on input pin \"in9\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in10\[1\] " "Warning: No output dependent on input pin \"in10\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in12\[1\] " "Warning: No output dependent on input pin \"in12\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in5\[1\] " "Warning: No output dependent on input pin \"in5\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in7\[1\] " "Warning: No output dependent on input pin \"in7\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in8\[1\] " "Warning: No output dependent on input pin \"in8\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in13\[1\] " "Warning: No output dependent on input pin \"in13\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in15\[1\] " "Warning: No output dependent on input pin \"in15\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in14\[1\] " "Warning: No output dependent on input pin \"in14\[1\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in3\[2\] " "Warning: No output dependent on input pin \"in3\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in2\[2\] " "Warning: No output dependent on input pin \"in2\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in4\[2\] " "Warning: No output dependent on input pin \"in4\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in9\[2\] " "Warning: No output dependent on input pin \"in9\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in10\[2\] " "Warning: No output dependent on input pin \"in10\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in12\[2\] " "Warning: No output dependent on input pin \"in12\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in5\[2\] " "Warning: No output dependent on input pin \"in5\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in7\[2\] " "Warning: No output dependent on input pin \"in7\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in8\[2\] " "Warning: No output dependent on input pin \"in8\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in13\[2\] " "Warning: No output dependent on input pin \"in13\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in15\[2\] " "Warning: No output dependent on input pin \"in15\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in14\[2\] " "Warning: No output dependent on input pin \"in14\[2\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in3\[3\] " "Warning: No output dependent on input pin \"in3\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in2\[3\] " "Warning: No output dependent on input pin \"in2\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in4\[3\] " "Warning: No output dependent on input pin \"in4\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in9\[3\] " "Warning: No output dependent on input pin \"in9\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in10\[3\] " "Warning: No output dependent on input pin \"in10\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in12\[3\] " "Warning: No output dependent on input pin \"in12\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in5\[3\] " "Warning: No output dependent on input pin \"in5\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in7\[3\] " "Warning: No output dependent on input pin \"in7\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in8\[3\] " "Warning: No output dependent on input pin \"in8\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in13\[3\] " "Warning: No output dependent on input pin \"in13\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in15\[3\] " "Warning: No output dependent on input pin \"in15\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "in14\[3\] " "Warning: No output dependent on input pin \"in14\[3\]\"" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "85 " "Info: Implemented 85 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "69 " "Info: Implemented 69 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "12 " "Info: Implemented 12 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 55 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 55 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 20 16:54:58 2006 " "Info: Processing ended: Wed Dec 20 16:54:58 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}