mux16_1.fnsim.qmsg

本程序实现了对输入数路的16选1功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 20 16:55:21 2006 " "Info: Processing started: Wed Dec 20 16:55:21 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mux16_1 -c mux16_1 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mux16_1 -c mux16_1 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux16_1.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file mux16_1.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux16_1 " "Info: Found entity 1: mux16_1" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 sel4m1 " "Info: Found entity 2: sel4m1" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mux16_1 " "Info: Elaborating entity \"mux16_1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "mout1 mux16_1.v(19) " "Warning (10235): Verilog HDL Always Construct warning at mux16_1.v(19): variable \"mout1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 19 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "mout2 mux16_1.v(20) " "Warning (10235): Verilog HDL Always Construct warning at mux16_1.v(20): variable \"mout2\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 20 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "mout3 mux16_1.v(21) " "Warning (10235): Verilog HDL Always Construct warning at mux16_1.v(21): variable \"mout3\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 21 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "mout4 mux16_1.v(22) " "Warning (10235): Verilog HDL Always Construct warning at mux16_1.v(22): variable \"mout4\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "mux16_1.v" "" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 22 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sel4m1 sel4m1:u1 " "Info: Elaborating entity \"sel4m1\" for hierarchy \"sel4m1:u1\"" {  } { { "mux16_1.v" "u1" { Text "F:/课程/SOC设计/作业/2sel16m1/mux16_1.v" 11 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 4 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 20 16:55:21 2006 " "Info: Processing ended: Wed Dec 20 16:55:21 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}