cnt60.txt

同步计数器和异步计数器在设计时有哪些区别？试用 六进制计数器和一个十进制计数器构成一个六十进制同步计数器。

十进制计数器：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
   port(clr : in std_logic;
        en : in std_logic;
        clk : in std_logic;
        cout : out std_logic;
        q: out std_logic_vector(3 downto 0));
end cnt10;
architecture rtl of cnt10 is
   signal q_tmp : std_logic_vector(3 downto 0);
begin
   process(clr,en,clk)
   begin
     if (clr = '1') then
           q_tmp <= (others => '0');
     elsif (clk'event and clk='1') then
        if (en = '1') then
            if (q_tmp = "1001") then
                 q_tmp <= (others => '0');
				cout <= '1';
            else
                 q_tmp <= q_tmp +1;
                 cout<='0';
            end if;
       end if;
    end if;
    q <= q_tmp;
  end process;
  end rtl;

六进制计数
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt6 is
   port(clr : in std_logic;
        en : in std_logic;
        clk : in std_logic;
        cout : out std_logic;
        q: out std_logic_vector(2  downto 0));
end cnt6;
architecture rtl of cnt6 is
   signal q_tmp : std_logic_vector(2 downto 0);
begin
   process(clr,en,clk)
   begin
     if (clr = '1') then
           q_tmp <= (others => '0');
     elsif (clk'event and clk='1') then
        if (en = '1') then
            if (q_tmp = "0101") then
                 q_tmp <= (others => '0');
				cout <= '1';
            else
                 q_tmp <= q_tmp +1;
                 cout<='0';
            end if;
       end if;
    end if;
    q <= q_tmp;
  end process;
  end rtl;

六十进制计数
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt60 is
   port(clr : in std_logic;
        en : in std_logic;
        clk : in std_logic;
        cout: out std_logic;
        q: out std_logic_vector(6 downto 0));
end cnt60;
architecture rtl of cnt60 is
  component cnt10
   port(clr : in std_logic;
        en : in std_logic;
        clk : in std_logic;
        cout : out std_logic;
        q: out std_logic_vector(3 downto 0));
  end component;
component cnt6
   port(clr : in std_logic;
        en : in std_logic;
        clk : in std_logic;
        cout : out std_logic;
        q: out std_logic_vector(2 downto 0));
  end component;
  signal reset,clk10,clr_tmp:std_logic;
begin
   u0:cnt10 port map(reset,en,clk,clk10,q(3 downto 0));
   u1:cnt10 port map(reset,en,clk10,cout,q(6 downto 4));
 end rtl;