📄 pll1.c
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/*
* Copyright 2002 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/
/* "@(#) DSP/BIOS 4.80.208 12-06-02 (barracuda-l19)" */
/******************************************************************************\
* Copyright (C) 2000 Texas Instruments Incorporated.
* All Rights Reserved
*------------------------------------------------------------------------------
* MODULE NAME... PLL
* FILENAME...... pll1.c
* DATE CREATED.. Tue 07/03/2001
* PROJECT....... Chip Support Library
* COMPONENT.....
* PREREQUISITS..
*------------------------------------------------------------------------------
* HISTORY:
* 07/03/2001 (IM) Created
*
*------------------------------------------------------------------------------
* DESCRIPTION:
*
* This is an example of the usage of PLL_setFreq function on C5509.
*
* The following assumptions for the PLL CLKMD fields were implemented
* in the PLL_setFreq() function:
* - IAI = 0; the PLL locks using the same process that was underway
* before the idle mode was entered.
* - IOB = 1; If the PLL indicates a break in the phase lock, it
* switches to its bypass mode and restarts the PLL
* phase-locking sequence.
* - PLLDIV = BYPASSDIV = div -1;
* - PLLENAB = 0 (bypass mode) if mul = 1, and 1 (PLL enabled) otherwise.
*
*
\******************************************************************************/
#include <csl.h>
#include <csl_pll.h>
main()
{
CSL_init();
PLL_setFreq(7,2); //multiplier = 7; Divisor = 2; PLL - enabled
asmtest();
}
/******************************************************************************\
* End of pll1.c
\******************************************************************************/
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