📄 startup33.lst
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214 ;
215 ; Stack Space for reentrant functions in the COMPACT model.
0000 216 PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
0000 217 PBPSTACKTOP EQU 0FFFFH+1; set top of stack to highest location+1.
218 ;
219 ;------------------------------------------------------------------------------
220 ;
221 ; Page Definition for Using the Compact Model with 64 KByte xdata RAM
222 ;
223 ; The following EQU statements define the xdata page used for pdata
224 ; variables. The EQU PPAGE must conform with the PPAGE control used
225 ; in the linker invocation.
226 ;
0000 227 PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.
228 ;
0000 229 PPAGE EQU 0 ; define PPAGE number.
230 ;
00A0 231 PPAGE_SFR DATA 0A0H ; SFR that supplies uppermost address byte
232 ; (most 8051 variants use P2 as uppermost address byte)
233 ;
234 ;------------------------------------------------------------------------------
235
236 ; Standard SFR Symbols
00E0 237 ACC DATA 0E0H
00F0 238 B DATA 0F0H
0081 239 SP DATA 81H
0082 240 DPL DATA 82H
0083 241 DPH DATA 83H
009D 242 BUSCON DATA 9DH
00A8 243 IE DATA 0A8H
244
245
246 NAME ?C_STARTUP
247
248
249 ?C_C51STARTUP SEGMENT CODE
250 ?STACK SEGMENT IDATA
251
---- 252 RSEG ?STACK
0000 253 DS 1
254
255 EXTRN CODE (?C_START)
256 PUBLIC ?C_STARTUP
A51 MACRO ASSEMBLER STARTUP33 07/11/2005 15:30:33 PAGE 5
257
---- 258 CSEG AT 0
0000 020000 F 259 ?C_STARTUP: LJMP STARTUP1 ; This is the POR reset vector
260
261 ; Turbo Debug Interrupt Service routine - Do Not Remove
262
---- 263 CSEG AT 063H ; debug interrupt vector
0063 53CFFD 264 ANL 0CFH,#0FDH ; clear debug interrupt request flag
0066 00 265 nop
0067 32 266 RETI
267
268
269
---- 270 RSEG ?C_C51STARTUP
0000 271 STARTUP1:
272
273 ; Turbo uPSD specific initialization - Set up BUSCON based on FREQ_OSC
274
275 IF (1) > 0 ; Check if a 5V or 3V Turbo uPSD device
276
0000 277 SETUP_BUSCON_5V:
278 IF (40000 ) > 24000 ; PFQ CLK Frequence 25-40MHz
0000 74C1 279 MOV A, #0C1H ; Initialize the BUSCON register
0002 F59D 280 MOV BUSCON, A ; BUSCON.7 = 1, Prefetch Queue is Enabled
281 ; BUSCON.6 = 1, Branch Cache is Enabled
282 ; BUSCON.5, BUSCON.4= 00B - 4 PFQCLK for Xdata Writ
e bus cycle
283 ; BUSCON.3, BUSCON.2= 00B - 4 PFQCLK for Xdata Read
bus cycle
284 ; BUSCON.1, BUSCON.0= 01B - 4 PFQCLK for Code Fetch
bus cycle
285 ELSE ; PFQ CLK Frequence 8-24MHz
MOV A, #0C0H ; Initialize the BUSCON register
MOV BUSCON, A ; BUSCON.7 = 1, Prefetch Queue is Enabled
; BUSCON.6 = 1, Branch Cache is Enabled
; BUSCON.5, BUSCON.4= 00B - 4 PFQCLK for Xdata Writ
e bus cycle
; BUSCON.3, BUSCON.2= 00B - 4 PFQCLK for Xdata Read
bus cycle
; BUSCON.1, BUSCON.0= 00B - 3 PFQCLK for Code Fetch
bus cycle
ENDIF
293
294 ELSE
SETUP_BUSCON_3V:
IF (40000 ) > 24000 ; PFQ CLK Frequence 25-40MHz
MOV A, #0D6H ; Initialize the BUSCON register
MOV BUSCON, A ; BUSCON.7 = 1, Prefetch Queue is Enabled
; BUSCON.6 = 1, Branch Cache is Enabled
; BUSCON.5, BUSCON.4= 01B - 5 PFQCLK for Xdata Writ
e bus cycle
; BUSCON.3, BUSCON.2= 01B - 5 PFQCLK for Xdata Read
bus cycle
; BUSCON.1, BUSCON.0= 10B - 5 PFQCLK for Code Fetch
bus cycle
ELSE ; PFQ CLK Frequence 8-24MHz
MOV A, #0C0H ; Initialize the BUSCON register
MOV BUSCON, A ; BUSCON.7 = 1, Prefetch Queue is Enabled
; BUSCON.6 = 1, Branch Cache is Enabled
; BUSCON.5, BUSCON.4= 00B - 4 PFQCLK for Xdata Writ
e bus cycle
; BUSCON.3, BUSCON.2= 00B - 4 PFQCLK for Xdata Read
bus cycle
; BUSCON.1, BUSCON.0= 00B - 3 PFQCLK for Code Fetch
bus cycle
ENDIF
A51 MACRO ASSEMBLER STARTUP33 07/11/2005 15:30:33 PAGE 6
ENDIF
312
313
314 ; Other Turbo Init code goes here...
315
0004 75A8C0 316 MOV IE, #0xC0 ; Enable Debug Interrupt
317
318 IF IDATALEN <> 0
0007 78FF 319 MOV R0,#IDATALEN - 1
0009 E4 320 CLR A
000A F6 321 IDATALOOP: MOV @R0,A
000B D8FD 322 DJNZ R0,IDATALOOP
323 ENDIF
324
325 IF XDATALEN <> 0
MOV DPTR,#XDATASTART
MOV R7,#LOW (XDATALEN)
IF (LOW (XDATALEN)) <> 0
MOV R6,#(HIGH (XDATALEN)) +1
ELSE
MOV R6,#HIGH (XDATALEN)
ENDIF
CLR A
XDATALOOP: MOVX @DPTR,A
INC DPTR
DJNZ R7,XDATALOOP
DJNZ R6,XDATALOOP
ENDIF
339
340 IF PPAGEENABLE <> 0
MOV PPAGE_SFR,#PPAGE
ENDIF
343
344 IF PDATALEN <> 0
MOV R0,#LOW (PDATASTART)
MOV R7,#LOW (PDATALEN)
CLR A
PDATALOOP: MOVX @R0,A
INC R0
DJNZ R7,PDATALOOP
ENDIF
352
353 IF IBPSTACK <> 0
EXTRN DATA (?C_IBP)
MOV ?C_IBP,#LOW IBPSTACKTOP
ENDIF
358
359 IF XBPSTACK <> 0
EXTRN DATA (?C_XBP)
MOV ?C_XBP,#HIGH XBPSTACKTOP
MOV ?C_XBP+1,#LOW XBPSTACKTOP
ENDIF
365
366 IF PBPSTACK <> 0
EXTRN DATA (?C_PBP)
MOV ?C_PBP,#LOW PBPSTACKTOP
ENDIF
370
000D 758100 F 371 MOV SP,#?STACK-1
372 ; This code is required if you use L51_BANK.A51 with Banking Mode 4
373 ; EXTRN CODE (?B_SWITCH0)
374 ; CALL ?B_SWITCH0 ; init bank mechanism to code bank 0
0010 020000 F 375 LJMP ?C_START
376
A51 MACRO ASSEMBLER STARTUP33 07/11/2005 15:30:33 PAGE 7
377
378
379 END
A51 MACRO ASSEMBLER STARTUP33 07/11/2005 15:30:33 PAGE 8
SYMBOL TABLE LISTING
------ ----- -------
N A M E T Y P E V A L U E ATTRIBUTES
?C_C51STARTUP. . . C SEG 0013H REL=UNIT
?C_START . . . . . C ADDR ----- EXT
?C_STARTUP . . . . C ADDR 0000H A
?STACK . . . . . . I SEG 0001H REL=UNIT
ACC. . . . . . . . D ADDR 00E0H A
B. . . . . . . . . D ADDR 00F0H A
BUSCON . . . . . . D ADDR 009DH A
DPH. . . . . . . . D ADDR 0083H A
DPL. . . . . . . . D ADDR 0082H A
IBPSTACK . . . . . N NUMB 0000H A
IBPSTACKTOP. . . . N NUMB 0100H A
IDATALEN . . . . . N NUMB 0100H A
IDATALOOP. . . . . C ADDR 000AH R SEG=?C_C51STARTUP
IE . . . . . . . . D ADDR 00A8H A
PBPSTACK . . . . . N NUMB 0000H A
PBPSTACKTOP. . . . N NUMB 0000H A
PDATALEN . . . . . N NUMB 0000H A
PDATASTART . . . . N NUMB 0000H A
PPAGE. . . . . . . N NUMB 0000H A
PPAGEENABLE. . . . N NUMB 0000H A
PPAGE_SFR. . . . . D ADDR 00A0H A
SETUP_BUSCON_5V. . C ADDR 0000H R SEG=?C_C51STARTUP
SP . . . . . . . . D ADDR 0081H A
STARTUP1 . . . . . C ADDR 0000H R SEG=?C_C51STARTUP
XBPSTACK . . . . . N NUMB 0000H A
XBPSTACKTOP. . . . N NUMB 0000H A
XDATALEN . . . . . N NUMB 0000H A
XDATASTART . . . . N NUMB 0000H A
REGISTER BANK(S) USED: 0
ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)
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