half_freq.v

来自「频率计源代码」· Verilog 代码 · 共 9 行

module Half_freq(CLK_in,CLK_out);
input CLK_in;
output CLK_out;
reg  CLK_out;
always@(posedge CLK_in)
begin
    CLK_out=~CLK_out;  
end
endmodule