test_vdo_adc_dac.vhd

hese files are for testing the Video ADC (TLV5734) and DAC THS8133 (DAC0). The ADC and DAC are te

--======================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--======================================================================================

--======================================================================================
entity Test_Vdo_Adc_Dac is
    Port ( clk : in std_logic;	  	-- 32 MHz clock
           reset : in std_logic;		-- Active High Reset(Push Button)

-------------------	ADC SIGNALS------------------------
		 
           Aout_ADC  : in std_logic_vector(7 downto 0);
           Bout_ADC  : in std_logic_vector(7 downto 0);
           Cout_ADC  : in std_logic_vector(7 downto 0);
           Mode0_ADC : out std_logic;
           Mode1_ADC : out std_logic;
		 Vdo_Adc_clk	 : out std_logic;
           Init_ADC 	 : out std_logic;
           Ext_clp_ADC   : out std_logic;
           G_Y_ADC 	 : out std_logic;

-------------------	DAC SIGNALS------------------------

           Ain_DAC 	 : out std_logic_vector(9 downto 0);
           Bin_DAC 	 : out std_logic_vector(9 downto 0);
           Cin_DAC 	 : out std_logic_vector(9 downto 0);
		 Dac_clk	 : out std_logic;
           Blank_DAC : out std_logic;
           Sync_DAC  : out std_logic;
           Sync_T 	 : out std_logic;
           Mode1_DAC : out std_logic;
           Mode2_DAC : out std_logic

		 );

end Test_Vdo_Adc_Dac;

--=======================================================================================
architecture Behavioral of Test_Vdo_Adc_Dac is
--=======================================================================================

type state is (start, en_init, dly, dis_init, stop);
signal ps, ns : state ;

signal  clk_div 	: std_logic_vector(3 downto 0);
signal  Aout_ADC_s 	: std_logic_vector(9 downto 0);
signal  Bout_ADC_s 	: std_logic_vector(9 downto 0);
signal  Cout_ADC_s 	: std_logic_vector(9 downto 0);

--======================================================================================
begin
--======================================================================================

 process(clk,reset)
 begin
 	if reset = '1' then
		clk_div <= (others => '0');
	elsif clk'event and clk = '1' then
		clk_div <= clk_div + 1;
	end if;
 end process;

--===================================ADC SIDE SIGNALS===================================

		Mode0_ADC <= '1';
          Mode1_ADC <= '0';
          Ext_clp_ADC   <= '0';
          G_Y_ADC 	 	<= '0';
		Vdo_Adc_clk   <= clk_div(3);

		Aout_ADC_s <= "00" & Aout_ADC ;
		Bout_ADC_s <= "00" & Bout_ADC ;
		Cout_ADC_s <= "00" & Cout_ADC ;


process(clk,reset)
begin
	if reset = '1' then
		ps <= start;
	elsif clk'event and clk = '1' then
		ps <= ns;
	end if;
end process;

process(ps)
begin
	case ps is 
		when start => 
			ns <= en_init;
   		when en_init => 
			ns <= dly;
		when dly => 
			ns <= stop;
		when stop => 
			ns <= stop;
		when others =>
			ns <= start;
	end case;
end process;


process(ps)
begin
	case ps is 
		when start => 
			Init_ADC <= '1';
   		when en_init => 
			Init_ADC <= '0';
		when dly => 
			Init_ADC <= '0';
		when stop => 
			Init_ADC <= '1';
		when others =>
			Init_ADC <= '1';
	end case;
end process;


--======================================DAC SIGNALS ====================================

          Blank_DAC <= '1';
          Sync_DAC  <= '1';
          Sync_T 	 <= '0';
          Mode1_DAC <= '0';
          Mode2_DAC <= '0';

		DAC_clk <= clk_div(3);

--======================================================================================

--process(clk,reset,Aout_ADC_s,Bout_ADC_s,Cout_ADC_s)
-- begin	
-- 	if reset <= '1' then
--		Ain_DAC <= (others => '0');
--		Bin_DAC <= (others => '0');
--		Cin_DAC <= (others => '0');
--	elsif clk'event and clk = '1' then
		Ain_DAC <=  Aout_ADC_s ;		
		Bin_DAC <=  Bout_ADC_s ;
		Cin_DAC <=  Cout_ADC_s ;
--	end if;
-- end process;

--======================================================================================
end Behavioral;
--======================================================================================