test_adc_dac.vhd

These files are for testing the ADC (AD9240) and DAC THS8133 (DAC1). The ADC and DAC are tested i

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity test_adc_dac is
port ( clk     : in std_logic; 
       rst     : in std_logic; 
--	  s      	: in std_logic;
       data    : in  std_logic_vector(13 downto 0);
--     otr     : in std_logic;
--     otr_out : out std_logic;
       adcclk  : out std_logic;

	MODE1_DAC1 : out std_logic;
	MODE2_DAC1 : out std_logic; 
	SYNC_T_DAC1 : out std_logic;
	SYNC_DAC1	 : out std_logic;
	CLK_DAC1	 : out std_logic;
	BLANK_DAC1 : out std_logic;

      dout    : out std_logic_vector(9 downto 0)
      );
end test_adc_dac;

architecture Behavioral of test_adc_dac is

signal divider : std_logic_vector(5 downto 0);
signal data_s  : std_logic_vector(13 downto 0);

begin

-- divide 32 Mhz to 1 Mhz  
process(rst,clk)
begin
  if(rst = '1') then
     divider <= (others => '0');
  elsif(clk'event and clk = '1') then
     divider <= divider + '1';
  end if;
end process;

	adcclk <= divider(3); -- 2 Mhz clk

   	data_s <= data;


dout     <= data_s(13 downto 4);


MODE1_DAC1    <= '0';
MODE2_DAC1    <= '0';
SYNC_T_DAC1   <= '0';
SYNC_DAC1	    <= '1';
CLK_DAC1	    <= divider(3);
BLANK_DAC1    <= '1';

end Behavioral;