decoder_time_post.vhd

16B20B编码转换

  signal lower_dec_fout_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_dec_fout_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_dec_fout_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_dec_fout_MC_D2 : STD_LOGIC; 
  signal decoded_data_3_MC_Q : STD_LOGIC; 
  signal decoded_data_3_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_3_MC_D : STD_LOGIC; 
  signal lower_dec_eout : STD_LOGIC; 
  signal decoded_data_3_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_3_MC_D1 : STD_LOGIC; 
  signal decoded_data_3_MC_D2 : STD_LOGIC; 
  signal decoded_data_3_MC_UIM : STD_LOGIC; 
  signal lower_dec_eout_MC_Q : STD_LOGIC; 
  signal lower_dec_eout_MC_D : STD_LOGIC; 
  signal lower_dec_eout_MC_D1 : STD_LOGIC; 
  signal lower_dec_eout_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_dec_err_chk_n003561 : STD_LOGIC; 
  signal N_PZ_180 : STD_LOGIC; 
  signal lower_dec_eout_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_dec_eout_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_dec_eout_MC_D2_PT_3 : STD_LOGIC; 
  signal N_PZ_304 : STD_LOGIC; 
  signal lower_dec_err_chk_n003564 : STD_LOGIC; 
  signal lower_dec_err_chk_n003574 : STD_LOGIC; 
  signal lower_dec_eout_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_dec_eout_MC_D2_PT_5 : STD_LOGIC; 
  signal serial_data_9_II_UIM : STD_LOGIC; 
  signal lower_dec_eout_MC_D2_PT_6 : STD_LOGIC; 
  signal serial_data_8_II_UIM : STD_LOGIC; 
  signal lower_dec_eout_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_dec_eout_MC_D2_PT_8 : STD_LOGIC; 
  signal lower_dec_eout_MC_D2_PT_9 : STD_LOGIC; 
  signal lower_dec_eout_MC_D2 : STD_LOGIC; 
  signal lower_dec_err_chk_n003561_MC_Q : STD_LOGIC; 
  signal lower_dec_err_chk_n003561_MC_D : STD_LOGIC; 
  signal lower_dec_err_chk_n003561_MC_D1 : STD_LOGIC; 
  signal lower_dec_err_chk_n003561_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_dec_err_chk_n003561_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_dec_err_chk_n003561_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_dec_err_chk_n003561_MC_D2 : STD_LOGIC; 
  signal N_PZ_304_MC_Q : STD_LOGIC; 
  signal N_PZ_304_MC_D : STD_LOGIC; 
  signal N_PZ_304_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_304_MC_D1 : STD_LOGIC; 
  signal N_PZ_304_MC_D2 : STD_LOGIC; 
  signal N_PZ_180_MC_Q : STD_LOGIC; 
  signal N_PZ_180_MC_D : STD_LOGIC; 
  signal N_PZ_180_MC_D1 : STD_LOGIC; 
  signal N_PZ_180_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_180_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_180_MC_D2 : STD_LOGIC; 
  signal lower_dec_err_chk_n003564_MC_Q : STD_LOGIC; 
  signal lower_dec_err_chk_n003564_MC_D : STD_LOGIC; 
  signal lower_dec_err_chk_n003564_MC_D1 : STD_LOGIC; 
  signal lower_dec_err_chk_n003564_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_dec_err_chk_n003564_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_dec_err_chk_n003564_MC_D2 : STD_LOGIC; 
  signal lower_dec_err_chk_n003574_MC_Q : STD_LOGIC; 
  signal lower_dec_err_chk_n003574_MC_D : STD_LOGIC; 
  signal lower_dec_err_chk_n003574_MC_D1 : STD_LOGIC; 
  signal lower_dec_err_chk_n003574_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_dec_err_chk_n003574_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_dec_err_chk_n003574_MC_D2 : STD_LOGIC; 
  signal decoded_data_4_MC_Q : STD_LOGIC; 
  signal decoded_data_4_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_4_MC_D : STD_LOGIC; 
  signal lower_dec_dout : STD_LOGIC; 
  signal decoded_data_4_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_4_MC_D1 : STD_LOGIC; 
  signal decoded_data_4_MC_D2 : STD_LOGIC; 
  signal decoded_data_4_MC_UIM : STD_LOGIC; 
  signal lower_dec_dout_MC_Q : STD_LOGIC; 
  signal lower_dec_dout_MC_D : STD_LOGIC; 
  signal lower_dec_dout_MC_D1 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2_PT_8 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2_PT_9 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2_PT_10 : STD_LOGIC; 
  signal lower_dec_dout_MC_D2 : STD_LOGIC; 
  signal decoded_data_5_MC_Q : STD_LOGIC; 
  signal decoded_data_5_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_5_MC_D : STD_LOGIC; 
  signal lower_dec_cout : STD_LOGIC; 
  signal decoded_data_5_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_5_MC_D1 : STD_LOGIC; 
  signal decoded_data_5_MC_D2 : STD_LOGIC; 
  signal decoded_data_5_MC_UIM : STD_LOGIC; 
  signal lower_dec_cout_MC_Q : STD_LOGIC; 
  signal lower_dec_cout_MC_D : STD_LOGIC; 
  signal lower_dec_cout_MC_D1 : STD_LOGIC; 
  signal lower_dec_cout_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_dec_cout_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_dec_cout_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_dec_cout_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_dec_cout_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_dec_cout_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_dec_cout_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_dec_cout_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_dec_cout_MC_D2_PT_8 : STD_LOGIC; 
  signal lower_dec_cout_MC_D2 : STD_LOGIC; 
  signal decoded_data_6_MC_Q : STD_LOGIC; 
  signal decoded_data_6_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_6_MC_D : STD_LOGIC; 
  signal lower_dec_bout : STD_LOGIC; 
  signal decoded_data_6_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_6_MC_D1 : STD_LOGIC; 
  signal decoded_data_6_MC_D2 : STD_LOGIC; 
  signal decoded_data_6_MC_UIM : STD_LOGIC; 
  signal lower_dec_bout_MC_Q : STD_LOGIC; 
  signal lower_dec_bout_MC_D : STD_LOGIC; 
  signal lower_dec_bout_MC_D1 : STD_LOGIC; 
  signal lower_dec_bout_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_dec_bout_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_dec_bout_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_dec_bout_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_dec_bout_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_dec_bout_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_dec_bout_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_dec_bout_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_dec_bout_MC_D2_PT_8 : STD_LOGIC; 
  signal lower_dec_bout_MC_D2_PT_9 : STD_LOGIC; 
  signal lower_dec_bout_MC_D2 : STD_LOGIC; 
  signal decoded_data_7_MC_Q : STD_LOGIC; 
  signal decoded_data_7_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_7_MC_D : STD_LOGIC; 
  signal lower_dec_aout : STD_LOGIC; 
  signal decoded_data_7_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_7_MC_D1 : STD_LOGIC; 
  signal decoded_data_7_MC_D2 : STD_LOGIC; 
  signal decoded_data_7_MC_UIM : STD_LOGIC; 
  signal lower_dec_aout_MC_Q : STD_LOGIC; 
  signal lower_dec_aout_MC_D : STD_LOGIC; 
  signal lower_dec_aout_MC_D1 : STD_LOGIC; 
  signal lower_dec_aout_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_dec_aout_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_dec_aout_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_dec_aout_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_dec_aout_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_dec_aout_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_dec_aout_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_dec_aout_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_dec_aout_MC_D2_PT_8 : STD_LOGIC; 
  signal lower_dec_aout_MC_D2_PT_9 : STD_LOGIC; 
  signal lower_dec_aout_MC_D2 : STD_LOGIC; 
  signal decoded_data_8_MC_Q : STD_LOGIC; 
  signal decoded_data_8_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_8_MC_D : STD_LOGIC; 
  signal upper_dec_hout : STD_LOGIC; 
  signal decoded_data_8_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_8_MC_D1 : STD_LOGIC; 
  signal decoded_data_8_MC_D2 : STD_LOGIC; 
  signal decoded_data_8_MC_UIM : STD_LOGIC; 
  signal upper_dec_hout_MC_Q : STD_LOGIC; 
  signal upper_dec_hout_MC_D : STD_LOGIC; 
  signal upper_dec_hout_MC_D1 : STD_LOGIC; 
  signal upper_dec_hout_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_dec_hout_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_dec_hout_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_dec_hout_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_dec_hout_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_dec_hout_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_dec_hout_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_dec_hout_MC_D2_PT_7 : STD_LOGIC; 
  signal upper_dec_hout_MC_D2_PT_8 : STD_LOGIC; 
  signal upper_dec_hout_MC_D2 : STD_LOGIC; 
  signal decoded_data_9_MC_Q : STD_LOGIC; 
  signal decoded_data_9_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal decoded_data_9_MC_D : STD_LOGIC; 
  signal upper_dec_gout : STD_LOGIC; 
  signal decoded_data_9_MC_D1_PT_0 : STD_LOGIC; 
  signal decoded_data_9_MC_D1 : STD_LOGIC; 
  signal decoded_data_9_MC_D2 : STD_LOGIC; 
  signal decoded_data_9_MC_UIM : STD_LOGIC; 
  signal upper_dec_gout_MC_Q : STD_LOGIC; 
  signal upper_dec_gout_MC_D : STD_LOGIC; 
  signal upper_dec_gout_MC_D1 : STD_LOGIC; 
  signal upper_dec_gout_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_dec_gout_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_dec_gout_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_dec_gout_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_dec_gout_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_dec_gout_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_dec_gout_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_dec_gout_MC_D2 : STD_LOGIC; 
  signal frame_out_dec_MC_Q : STD_LOGIC; 
  signal frame_out_dec_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal frame_out_dec_MC_D : STD_LOGIC; 
  signal frame_out_dec_MC_D1_PT_0 : STD_LOGIC; 
  signal frame_out_dec_MC_D1 : STD_LOGIC; 
  signal frame_out_dec_MC_D2 : STD_LOGIC; 
  signal ill_char_det_MC_Q : STD_LOGIC; 
  signal ill_char_det_MC_Q_tsim_ireg_Q : STD_LOGIC; 
  signal ill_char_det_MC_D : STD_LOGIC; 
  signal err_prs_state_ffd1 : STD_LOGIC; 
  signal err_prs_state_ffd2 : STD_LOGIC; 
  signal err_ill_char_det7 : STD_LOGIC; 
  signal ill_char_det_MC_D1_PT_0 : STD_LOGIC; 
  signal ill_char_det_MC_D1 : STD_LOGIC; 
  signal ill_char_det_MC_D2 : STD_LOGIC; 
  signal err_prs_state_ffd1_MC_Q : STD_LOGIC; 
  signal err_prs_state_ffd1_MC_R_OR_PRLD : STD_LOGIC; 
  signal err_prs_state_ffd1_MC_D : STD_LOGIC; 
  signal err_prs_state_ffd1_MC_D1 : STD_LOGIC; 
  signal err_prs_state_ffd1_MC_D2_PT_0 : STD_LOGIC; 
  signal err_prs_state_ffd1_MC_D2_PT_1 : STD_LOGIC; 
  signal err_prs_state_ffd1_MC_D2 : STD_LOGIC; 
  signal err_prs_state_ffd2_MC_Q : STD_LOGIC; 
  signal err_prs_state_ffd2_MC_R_OR_PRLD : STD_LOGIC; 
  signal err_prs_state_ffd2_MC_D : STD_LOGIC; 
  signal err_prs_state_ffd2_MC_D1 : STD_LOGIC; 
  signal err_prs_state_ffd2_MC_D2_PT_0 : STD_LOGIC; 
  signal err_prs_state_ffd2_MC_D2_PT_1 : STD_LOGIC; 
  signal err_prs_state_ffd2_MC_D2 : STD_LOGIC; 
  signal err_ill_char_det7_MC_Q : STD_LOGIC; 
  signal err_ill_char_det7_MC_D : STD_LOGIC; 
  signal err_ill_char_det7_MC_D1 : STD_LOGIC; 
  signal err_n0020 : STD_LOGIC; 
  signal error_u : STD_LOGIC; 
  signal err_ill_char_det5 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_0 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_217 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_2 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_3 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_4 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_5 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_6 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_7 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_8 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_9 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_10 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_11 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_12 : STD_LOGIC; 
  signal err_ill_char_det7_MC_D2_PT_13 : STD_LOGIC;