application.rpt

3层电梯的控制

LC25 -> * * * * * * * * * - - - - | - * | <-- |cabine:Commande|EtatPresent1
LC29 -> * * * * * * * * * - - - - | - * | <-- |cabine:Commande|EtatPresent0
LC26 -> - - - * - - - - - - - - - | - * | <-- |cabine:Commande|~1325~1
LC27 -> - - - - * - - - - - - - - | - * | <-- |cabine:Commande|~1331~1
LC22 -> - - - - - * - - - - - - - | - * | <-- |cabine:Commande|~1337~1
LC19 -> * * - - - - - - - * - - - | - * | <-- |securite:Mem|~27~1
LC20 -> * * - - - - - - - * * * * | - * | <-- |securite:Mem|~29~1
LC21 -> * * - - - - - - - * * * * | - * | <-- |securite:Mem|~33~1
LC28 -> * * - - - - - - - * * * * | - * | <-- |securite:Mem|~35~1

Pin
16   -> - - - * * * * - * - - - - | - * | <-- AppelPalier1
14   -> - - * * * * * * * - - - - | - * | <-- AppelPalier2
13   -> - - * * * * * * * - - - - | - * | <-- AppelPalier3
12   -> - - - - - - * * * - - - - | - * | <-- AppelPalier4
11   -> - - - - - - - - - - * * - | - * | <-- Arret
4    -> * - - - - * - - - - - - - | - * | <-- CapteurEtage1
5    -> * * - - - - * - * - - - - | - * | <-- CapteurEtage2
6    -> * * * * - - - * * - - - - | - * | <-- CapteurEtage3
7    -> - * * * - * - - - - - - - | - * | <-- CapteurEtage4
43   -> - - - - - - - - - - - - - | - - | <-- clk
8    -> - - * * * * * * * - - - - | - * | <-- Porteouverte
9    -> - - - - - - - - - - - * * | - * | <-- Reprise


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           e:\vhdl\application.rpt
application

** EQUATIONS **

AppelPalier1 : INPUT;
AppelPalier2 : INPUT;
AppelPalier3 : INPUT;
AppelPalier4 : INPUT;
Arret    : INPUT;
CapteurEtage1 : INPUT;
CapteurEtage2 : INPUT;
CapteurEtage3 : INPUT;
CapteurEtage4 : INPUT;
clk      : INPUT;
Porteouverte : INPUT;
Reprise  : INPUT;

-- Node name is 'ActionDescente1' 
-- Equation name is 'ActionDescente1', location is LC017, type is output.
 ActionDescente1 = LCELL( _EQ001 $  GND);
  _EQ001 = !CapteurEtage2 & !_LC023 &  _LC024 &  _LC025 &  _LC029 &  _X001
         # !CapteurEtage3 &  _LC023 & !_LC024 & !_LC025 &  _LC029 &  _X001
         # !CapteurEtage1 & !_LC023 & !_LC024 & !_LC025 & !_LC029 &  _X001;
  _X001  = EXP( _LC019 & !_LC020 & !_LC021 & !_LC028);

-- Node name is 'ActionMontee1' 
-- Equation name is 'ActionMontee1', location is LC018, type is output.
 ActionMontee1 = LCELL( _EQ002 $  GND);
  _EQ002 = !CapteurEtage4 & !_LC023 &  _LC024 & !_LC025 &  _LC029 &  _X001
         # !CapteurEtage3 & !_LC023 &  _LC024 & !_LC025 & !_LC029 &  _X001
         # !CapteurEtage2 & !_LC023 & !_LC024 &  _LC025 & !_LC029 &  _X001;
  _X001  = EXP( _LC019 & !_LC020 & !_LC021 & !_LC028);

-- Node name is '|cabine:Commande|:16' = '|cabine:Commande|EtatPresent0' 
-- Equation name is '_LC029', type is buried 
_LC029   = TFFE(!_EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !_LC022 &  _X002 &  _X003 &  _X004 &  _X005 &  _X006 &  _X007;
  _X002  = EXP( CapteurEtage4 & !_LC023 &  _LC024 & !_LC025 &  _LC029 & 
              Porteouverte);
  _X003  = EXP( AppelPalier1 & !_LC023 & !_LC024 &  _LC025 &  _LC029 & 
             !Porteouverte);
  _X004  = EXP( AppelPalier2 & !_LC023 & !_LC024 & !_LC025 &  _LC029 & 
             !Porteouverte);
  _X005  = EXP( AppelPalier2 &  _LC023 & !_LC024 & !_LC025 & !_LC029 & 
             !Porteouverte);
  _X006  = EXP( CapteurEtage1 & !_LC023 & !_LC024 & !_LC025 & !_LC029 & 
              Porteouverte);
  _X007  = EXP( AppelPalier3 & !_LC023 & !_LC024 &  _LC029 & !Porteouverte);

-- Node name is '|cabine:Commande|:15' = '|cabine:Commande|EtatPresent1' 
-- Equation name is '_LC025', type is buried 
_LC025   = TFFE(!_EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 = !_LC027 &  _X003 &  _X004 &  _X008 &  _X009;
  _X003  = EXP( AppelPalier1 & !_LC023 & !_LC024 &  _LC025 &  _LC029 & 
             !Porteouverte);
  _X004  = EXP( AppelPalier2 & !_LC023 & !_LC024 & !_LC025 &  _LC029 & 
             !Porteouverte);
  _X008  = EXP( AppelPalier1 & !AppelPalier2 & !_LC023 &  _LC024 &  _LC025 & 
             !_LC029 & !Porteouverte);
  _X009  = EXP( AppelPalier2 & !AppelPalier3 &  _LC023 & !_LC024 & !_LC025 & 
             !_LC029 & !Porteouverte);

-- Node name is '|cabine:Commande|:14' = '|cabine:Commande|EtatPresent2' 
-- Equation name is '_LC024', type is buried 
_LC024   = TFFE(!_EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !_LC026 &  _X002 &  _X008 &  _X009 &  _X010 &  _X011;
  _X002  = EXP( CapteurEtage4 & !_LC023 &  _LC024 & !_LC025 &  _LC029 & 
              Porteouverte);
  _X008  = EXP( AppelPalier1 & !AppelPalier2 & !_LC023 &  _LC024 &  _LC025 & 
             !_LC029 & !Porteouverte);
  _X009  = EXP( AppelPalier2 & !AppelPalier3 &  _LC023 & !_LC024 & !_LC025 & 
             !_LC029 & !Porteouverte);
  _X010  = EXP( CapteurEtage3 &  _LC023 & !_LC024 &  _LC025 &  Porteouverte);
  _X011  = EXP( CapteurEtage3 &  _LC023 & !_LC024 &  _LC029 &  Porteouverte);

-- Node name is '|cabine:Commande|:13' = '|cabine:Commande|EtatPresent3' 
-- Equation name is '_LC023', type is buried 
_LC023   = TFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  AppelPalier2 & !AppelPalier3 &  _LC023 & !_LC024 & !_LC025 & 
             !_LC029 & !Porteouverte
         #  CapteurEtage4 & !_LC023 &  _LC024 & !_LC025 &  _LC029 & 
              Porteouverte
         #  CapteurEtage3 &  _LC023 &  _LC029 &  Porteouverte
         #  CapteurEtage3 &  _LC023 &  _LC024 &  Porteouverte
         #  CapteurEtage3 &  _LC023 &  _LC025 &  Porteouverte;

-- Node name is '|cabine:Commande|~1325~1' 
-- Equation name is '_LC026', type is buried 
-- synthesized logic cell 
_LC026   = LCELL( _EQ007 $  GND);
  _EQ007 = !AppelPalier1 &  AppelPalier3 & !_LC023 & !_LC024 &  _LC025 & 
              _LC029 & !Porteouverte
         # !AppelPalier1 &  AppelPalier4 & !_LC023 & !_LC024 &  _LC025 & 
              _LC029 & !Porteouverte
         # !AppelPalier2 &  AppelPalier3 & !_LC023 & !_LC024 & !_LC025 & 
              _LC029 & !Porteouverte
         # !AppelPalier2 &  AppelPalier4 & !_LC023 & !_LC024 & !_LC025 & 
              _LC029 & !Porteouverte
         #  CapteurEtage2 & !_LC023 &  _LC024 &  _LC025 &  _LC029 & 
              Porteouverte;

-- Node name is '|cabine:Commande|~1331~1' 
-- Equation name is '_LC027', type is buried 
-- synthesized logic cell 
_LC027   = LCELL( _EQ008 $  GND);
  _EQ008 = !AppelPalier2 &  AppelPalier4 & !_LC023 &  _LC024 &  _LC025 & 
             !_LC029 & !Porteouverte
         #  AppelPalier3 & !_LC023 & !_LC024 &  _LC025 &  _LC029 & 
             !Porteouverte
         #  AppelPalier4 & !_LC023 & !_LC024 &  _LC025 &  _LC029 & 
             !Porteouverte
         #  CapteurEtage3 &  _LC023 & !_LC025 &  _LC029 &  Porteouverte
         #  CapteurEtage3 &  _LC024 & !_LC025 & !_LC029 &  Porteouverte;

-- Node name is '|cabine:Commande|~1337~1' 
-- Equation name is '_LC022', type is buried 
-- synthesized logic cell 
_LC022   = LCELL( _EQ009 $  GND);
  _EQ009 =  CapteurEtage3 &  _LC023 &  _LC029 &  Porteouverte
         # !AppelPalier1 &  AppelPalier4 & !_LC023 &  _LC024 &  _LC025 & 
             !_LC029 & !Porteouverte
         #  CapteurEtage2 & !_LC023 & !_LC024 &  _LC025 & !_LC029 & 
              Porteouverte
         #  AppelPalier2 & !_LC023 &  _LC024 &  _LC025 & !_LC029 & 
             !Porteouverte
         #  AppelPalier3 &  _LC023 & !_LC024 & !_LC025 & !_LC029 & 
             !Porteouverte;

-- Node name is '|securite:Mem|~27~1' 
-- Equation name is '_LC019', type is buried 
-- synthesized logic cell 
_LC019   = LCELL( _EQ010 $  VCC);
  _EQ010 = !_LC019 & !_LC020 & !_LC021 & !_LC028;

-- Node name is '|securite:Mem|~29~1' 
-- Equation name is '_LC020', type is buried 
-- synthesized logic cell 
_LC020   = LCELL( _EQ011 $ !Arret);
  _EQ011 = !Arret & !_LC020 & !_LC021 & !_LC028;

-- Node name is '|securite:Mem|~33~1' 
-- Equation name is '_LC021', type is buried 
-- synthesized logic cell 
_LC021   = LCELL( _EQ012 $  GND);
  _EQ012 = !Arret & !_LC020 & !_LC021 & !_LC028 &  Reprise;

-- Node name is '|securite:Mem|~35~1' 
-- Equation name is '_LC028', type is buried 
-- synthesized logic cell 
_LC028   = LCELL( _EQ013 $  Reprise);
  _EQ013 = !_LC020 & !_LC021 & !_LC028 &  Reprise;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                    e:\vhdl\application.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,433K