cabine.rpt

3层电梯的控制

LC23 -> - - - - - * - - - | - * | <-- ~1337~1

Pin
5    -> - - - * * * * - * | - * | <-- AP1
11   -> - - * * * * * * * | - * | <-- AP2
13   -> - - * * * * * * * | - * | <-- AP3
12   -> - - - - - - * * * | - * | <-- AP4
9    -> * - - - - * - - - | - * | <-- ET1
8    -> * * - - - - * - * | - * | <-- ET2
7    -> * * * * - - - * * | - * | <-- ET3
6    -> - * * * - * - - - | - * | <-- ET4
43   -> - - - - - - - - - | - - | <-- horloge
4    -> - - * * * * * * * | - * | <-- p


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                e:\vhdl\cabine.rpt
cabine

** EQUATIONS **

AP1      : INPUT;
AP2      : INPUT;
AP3      : INPUT;
AP4      : INPUT;
ET1      : INPUT;
ET2      : INPUT;
ET3      : INPUT;
ET4      : INPUT;
horloge  : INPUT;
p        : INPUT;

-- Node name is 'D' 
-- Equation name is 'D', location is LC025, type is output.
 D       = LCELL( _EQ001 $  GND);
  _EQ001 =  EtatPresent0 &  EtatPresent1 &  EtatPresent2 & !EtatPresent3 & 
             !ET2
         #  EtatPresent0 & !EtatPresent1 & !EtatPresent2 &  EtatPresent3 & 
             !ET3
         # !EtatPresent0 & !EtatPresent1 & !EtatPresent2 & !EtatPresent3 & 
             !ET1;

-- Node name is ':16' = 'EtatPresent0' 
-- Equation name is 'EtatPresent0', location is LC019, type is buried.
EtatPresent0 = TFFE(!_EQ002, GLOBAL( horloge),  VCC,  VCC,  VCC);
  _EQ002 = !_LC023 &  _X001 &  _X002 &  _X003 &  _X004 &  _X005 &  _X006;
  _X001  = EXP( EtatPresent0 & !EtatPresent1 &  EtatPresent2 & !EtatPresent3 & 
              ET4 &  p);
  _X002  = EXP( AP1 &  EtatPresent0 &  EtatPresent1 & !EtatPresent2 & 
             !EtatPresent3 & !p);
  _X003  = EXP( AP2 &  EtatPresent0 & !EtatPresent1 & !EtatPresent2 & 
             !EtatPresent3 & !p);
  _X004  = EXP( AP2 & !EtatPresent0 & !EtatPresent1 & !EtatPresent2 & 
              EtatPresent3 & !p);
  _X005  = EXP(!EtatPresent0 & !EtatPresent1 & !EtatPresent2 & !EtatPresent3 & 
              ET1 &  p);
  _X006  = EXP( AP3 &  EtatPresent0 & !EtatPresent2 & !EtatPresent3 & !p);

-- Node name is ':15' = 'EtatPresent1' 
-- Equation name is 'EtatPresent1', location is LC020, type is buried.
EtatPresent1 = TFFE(!_EQ003, GLOBAL( horloge),  VCC,  VCC,  VCC);
  _EQ003 = !_LC017 &  _X002 &  _X003 &  _X007 &  _X008;
  _X002  = EXP( AP1 &  EtatPresent0 &  EtatPresent1 & !EtatPresent2 & 
             !EtatPresent3 & !p);
  _X003  = EXP( AP2 &  EtatPresent0 & !EtatPresent1 & !EtatPresent2 & 
             !EtatPresent3 & !p);
  _X007  = EXP( AP1 & !AP2 & !EtatPresent0 &  EtatPresent1 &  EtatPresent2 & 
             !EtatPresent3 & !p);
  _X008  = EXP( AP2 & !AP3 & !EtatPresent0 & !EtatPresent1 & !EtatPresent2 & 
              EtatPresent3 & !p);

-- Node name is ':14' = 'EtatPresent2' 
-- Equation name is 'EtatPresent2', location is LC021, type is buried.
EtatPresent2 = TFFE(!_EQ004, GLOBAL( horloge),  VCC,  VCC,  VCC);
  _EQ004 = !_LC018 &  _X001 &  _X007 &  _X008 &  _X009 &  _X010;
  _X001  = EXP( EtatPresent0 & !EtatPresent1 &  EtatPresent2 & !EtatPresent3 & 
              ET4 &  p);
  _X007  = EXP( AP1 & !AP2 & !EtatPresent0 &  EtatPresent1 &  EtatPresent2 & 
             !EtatPresent3 & !p);
  _X008  = EXP( AP2 & !AP3 & !EtatPresent0 & !EtatPresent1 & !EtatPresent2 & 
              EtatPresent3 & !p);
  _X009  = EXP( EtatPresent1 & !EtatPresent2 &  EtatPresent3 &  ET3 &  p);
  _X010  = EXP( EtatPresent0 & !EtatPresent2 &  EtatPresent3 &  ET3 &  p);

-- Node name is ':13' = 'EtatPresent3' 
-- Equation name is 'EtatPresent3', location is LC022, type is buried.
EtatPresent3 = TFFE( _EQ005, GLOBAL( horloge),  VCC,  VCC,  VCC);
  _EQ005 =  AP2 & !AP3 & !EtatPresent0 & !EtatPresent1 & !EtatPresent2 & 
              EtatPresent3 & !p
         #  EtatPresent0 & !EtatPresent1 &  EtatPresent2 & !EtatPresent3 & 
              ET4 &  p
         #  EtatPresent0 &  EtatPresent3 &  ET3 &  p
         #  EtatPresent2 &  EtatPresent3 &  ET3 &  p
         #  EtatPresent1 &  EtatPresent3 &  ET3 &  p;

-- Node name is 'M' 
-- Equation name is 'M', location is LC024, type is output.
 M       = LCELL( _EQ006 $  GND);
  _EQ006 =  EtatPresent0 & !EtatPresent1 &  EtatPresent2 & !EtatPresent3 & 
             !ET4
         # !EtatPresent0 & !EtatPresent1 &  EtatPresent2 & !EtatPresent3 & 
             !ET3
         # !EtatPresent0 &  EtatPresent1 & !EtatPresent2 & !EtatPresent3 & 
             !ET2;

-- Node name is '~1325~1' 
-- Equation name is '~1325~1', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL( _EQ007 $  GND);
  _EQ007 = !AP1 &  AP3 &  EtatPresent0 &  EtatPresent1 & !EtatPresent2 & 
             !EtatPresent3 & !p
         # !AP1 &  AP4 &  EtatPresent0 &  EtatPresent1 & !EtatPresent2 & 
             !EtatPresent3 & !p
         # !AP2 &  AP3 &  EtatPresent0 & !EtatPresent1 & !EtatPresent2 & 
             !EtatPresent3 & !p
         # !AP2 &  AP4 &  EtatPresent0 & !EtatPresent1 & !EtatPresent2 & 
             !EtatPresent3 & !p
         #  EtatPresent0 &  EtatPresent1 &  EtatPresent2 & !EtatPresent3 & 
              ET2 &  p;

-- Node name is '~1331~1' 
-- Equation name is '~1331~1', location is LC017, type is buried.
-- synthesized logic cell 
_LC017   = LCELL( _EQ008 $  GND);
  _EQ008 = !AP2 &  AP4 & !EtatPresent0 &  EtatPresent1 &  EtatPresent2 & 
             !EtatPresent3 & !p
         #  AP3 &  EtatPresent0 &  EtatPresent1 & !EtatPresent2 & 
             !EtatPresent3 & !p
         #  AP4 &  EtatPresent0 &  EtatPresent1 & !EtatPresent2 & 
             !EtatPresent3 & !p
         #  EtatPresent0 & !EtatPresent1 &  EtatPresent3 &  ET3 &  p
         # !EtatPresent0 & !EtatPresent1 &  EtatPresent2 &  ET3 &  p;

-- Node name is '~1337~1' 
-- Equation name is '~1337~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ009 $  GND);
  _EQ009 =  EtatPresent0 &  EtatPresent3 &  ET3 &  p
         # !AP1 &  AP4 & !EtatPresent0 &  EtatPresent1 &  EtatPresent2 & 
             !EtatPresent3 & !p
         # !EtatPresent0 &  EtatPresent1 & !EtatPresent2 & !EtatPresent3 & 
              ET2 &  p
         #  AP2 & !EtatPresent0 &  EtatPresent1 &  EtatPresent2 & 
             !EtatPresent3 & !p
         #  AP3 & !EtatPresent0 & !EtatPresent1 & !EtatPresent2 & 
              EtatPresent3 & !p;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                         e:\vhdl\cabine.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,380K