📄 cabine.rpt
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Project Information e:\vhdl\cabine.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/15/2005 03:26:00
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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***** Project compilation was successful
CABINE
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
cabine EPM7032LC44-6 10 2 0 9 10 28 %
User Pins: 10 2 0
Project Information e:\vhdl\cabine.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'horloge' chosen for auto global Clock
Device-Specific Information: e:\vhdl\cabine.rpt
cabine
***** Logic for device 'cabine' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R R
h E E
o S S
r E E
l R R
E A V G G G o G V V
T P C N N N g N E E
4 1 p C D D D e D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
ET3 | 7 39 | RESERVED
ET2 | 8 38 | RESERVED
ET1 | 9 37 | RESERVED
GND | 10 36 | RESERVED
AP2 | 11 35 | VCC
AP4 | 12 EPM7032LC44-6 34 | RESERVED
AP3 | 13 33 | M
RESERVED | 14 32 | D
VCC | 15 31 | RESERVED
RESERVED | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R R
E E E E N C E E E E E
S S S S D C S S S S S
E E E E E E E E E
R R R R R R R R R
V V V V V V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\vhdl\cabine.rpt
cabine
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 9/16( 56%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 9/16( 56%) 2/16( 12%) 14/16( 87%) 16/36( 44%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 11/32 ( 34%)
Total logic cells used: 9/32 ( 28%)
Total shareable expanders used: 10/32 ( 31%)
Total Turbo logic cells used: 9/32 ( 28%)
Total shareable expanders not available (n/a): 4/32 ( 12%)
Average fan-in: 9.77
Total fan-in: 88
Total input pins required: 10
Total output pins required: 2
Total bidirectional pins required: 0
Total logic cells required: 9
Total flipflops required: 4
Total product terms required: 39
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 10
Synthesized logic cells: 3/ 32 ( 9%)
Device-Specific Information: e:\vhdl\cabine.rpt
cabine
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
5 (2) (A) INPUT 0 0 0 0 0 0 5 AP1
11 (7) (A) INPUT 0 0 0 0 0 0 7 AP2
13 (9) (A) INPUT 0 0 0 0 0 0 7 AP3
12 (8) (A) INPUT 0 0 0 0 0 0 3 AP4
9 (6) (A) INPUT 0 0 0 0 0 1 1 ET1
8 (5) (A) INPUT 0 0 0 0 0 2 2 ET2
7 (4) (A) INPUT 0 0 0 0 0 2 4 ET3
6 (3) (A) INPUT 0 0 0 0 0 1 3 ET4
43 - - INPUT G 0 0 0 0 0 0 0 horloge
4 (1) (A) INPUT 0 0 0 0 0 0 7 p
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\vhdl\cabine.rpt
cabine
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
32 25 B OUTPUT t 0 0 0 3 4 0 0 D
33 24 B OUTPUT t 0 0 0 3 4 0 0 M
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdl\cabine.rpt
cabine
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(36) 22 B TFFE + t 1 0 1 5 4 2 7 EtatPresent3 (:13)
(37) 21 B TFFE + t 5 3 0 6 5 2 7 EtatPresent2 (:14)
(38) 20 B TFFE + t 4 4 0 4 5 2 7 EtatPresent1 (:15)
(39) 19 B TFFE + t 6 3 0 6 5 2 7 EtatPresent0 (:16)
(40) 18 B SOFT s t 1 0 1 6 4 0 1 ~1325~1
(41) 17 B SOFT s t 1 0 1 5 4 0 1 ~1331~1
(34) 23 B SOFT s t 1 0 1 7 4 0 1 ~1337~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdl\cabine.rpt
cabine
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------- LC25 D
| +--------------- LC24 M
| | +------------- LC22 EtatPresent3
| | | +----------- LC21 EtatPresent2
| | | | +--------- LC20 EtatPresent1
| | | | | +------- LC19 EtatPresent0
| | | | | | +----- LC18 ~1325~1
| | | | | | | +--- LC17 ~1331~1
| | | | | | | | +- LC23 ~1337~1
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC22 -> * * * * * * * * * | - * | <-- EtatPresent3
LC21 -> * * * * * * * * * | - * | <-- EtatPresent2
LC20 -> * * * * * * * * * | - * | <-- EtatPresent1
LC19 -> * * * * * * * * * | - * | <-- EtatPresent0
LC18 -> - - - * - - - - - | - * | <-- ~1325~1
LC17 -> - - - - * - - - - | - * | <-- ~1331~1
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