comp_altera_lib.do

这个verilog代码是一个输入输出经典的例子。大家一起参考。

if [file exists $env(QUARTUS_ROOTDIR)/eda/sim_lib/stratix_atoms.v] {

    echo *** Compiling stratix_atoms.v into stratix library ...
    vlog -work stratix $env(QUARTUS_ROOTDIR)/eda/sim_lib/stratix_atoms.v

} else {

    echo *** Unable to locate Altera simulation models

}