_primary.vhd

来自「这个verilog代码是一个输入输出经典的例子。大家一起参考。」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity stratix_asynch_io is
    generic(
        operation_mode  : string  := "input";
        bus_hold        : string  := "false";
        open_drain_output: string  := "false"
    );
    port(
        datain          : in     vl_logic;
        oe              : in     vl_logic;
        regin           : in     vl_logic;
        ddioregin       : in     vl_logic;
        padio           : inout  vl_logic;
        combout         : out    vl_logic;
        regout          : out    vl_logic;
        ddioregout      : out    vl_logic
    );
end stratix_asynch_io;