_primary.vhd

这个verilog代码是一个输入输出经典的例子。大家一起参考。

library verilog;
use verilog.vl_types.all;
entity scale_cntr is
    port(
        clk             : in     vl_logic;
        pll_reset       : in     vl_logic;
        internal_reset  : in     vl_logic;
        cout            : out    vl_logic;
        high            : in     vl_logic_vector(31 downto 0);
        low             : in     vl_logic_vector(31 downto 0);
        initial_value   : in     vl_logic_vector(31 downto 0);
        mode            : in     vl_logic_vector(48 downto 1);
        time_delay      : in     vl_logic_vector(31 downto 0);
        ph_tap          : in     vl_logic_vector(31 downto 0)
    );
end scale_cntr;