📄 分频.txt
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk:in std_logic;
clk1k,clk100,clk1:out std_logic);
end fenpin;
architecture a of fenpin is
signal count:integer range 0 to 999;
signal count1:integer range 0 to 9;
signal count2:integer range 0 to 99;
signal m,n:std_logic;
begin
p1: process(clk)
begin
if(clk'event and clk='1')then
if(count=999) then count<=0;
else count<=count+1;
end if;
if(count<500) then m<='1';
else m<='0';
end if;
end if;
end process;
p2:process(m)
begin
if(m'event and m='1') then
if(count1=9)then count1<=0;
else count1<=count1+1;
end if;
if(count1<5)then n<='1';
else n<='0';
end if;
end if;
end process;
p3:process(n)
begin
if(n'event and n='1')then
if(count2=99)then count2<=0;
else count2<=count2+1;
end if;
if(count2<50)then clk1<='1';
else clk1<='0';
end if;
end if;
end process;
clk1k<=m;
clk100<=n;
end;
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