📄 顶层文件.txt
字号:
library ieee;
use ieee.std_logic_1164.all;
entity final is
port(clk:in std_logic;
change:in std_logic;
seg:out std_logic_vector(6 downto 0);
sel:out std_logic_vector(3 downto 0);
light1:out std_logic_vector(2 downto 0);
light2:out std_logic_vector(2 downto 0));
end final;
architecture a of final is
signal cp1k,cp100,cp1:std_logic;
signal re1,ch1:std_logic;
signal number:integer range 0 to 9;
component fenpin
port(clk:in std_logic;
clk1k,clk100,clk1:out std_logic);
end component;
component fangdou
port(clk100:in std_logic;
keyin:in std_logic;
keyout:out std_logic);
end component;
component traffic
port(clk1,clk1k:in std_logic;
change:in std_logic;
light1:out std_logic_vector(2 downto 0);
light2:out std_logic_vector(2 downto 0);
sel:out std_logic_vector(3 downto 0);
seg:out std_logic_vector(6 downto 0));
end component;
begin
u1:fenpin port map(clk,cp1k,cp100,cp1);
u2:fangdou port map(cp100,change,ch1);
u3:traffic port map(cp1,cp1k,ch1,light1,light2,sel,seg);
end;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -