read_timingsheet_0.xls

arm控制FPGA的DDR测试代码

Uncertainity parameter                     	Value                                  	Uncertainity before DQS             	Uncertainity after DQS              	Meaning
Tclock                                     	7518.80                           	                                        	                                        	clock period
Tmemory_dll_duty_cycle_dist                	375.94      	375.94                          	375.94                          	Duty cycle distortion from memory DLL is subtracted from clock phase(equal to halfclock period) to determine Tdata_period
Tdata_period                               	3383.46                    	                                        	                                        	Data period is half the clock period with 10% duty cycle duty distortion subtracted from it
Memory uncertanities                       	750                           	750                           	750                           	This parameter considers the worst of all the memory parameters since there is voerlap between these parameters(Tdsq,Tqhs,Tdqsk,Tac
Skew between DQS to DQ                     	0                      	0                          	0                          	Due to overlap with other memory parameters.Only the worst case parameter Tac being considered
Data Hold skew factor                      	0                   	0                     	0                     	Due to overlap with other memory parameters.Only the worst case parameter Tac being considered
Tpackage_skew                              	90                    	45                        	45                        	Package skew
Data setup time with respect to DQS        	0                   	0                	0                	DQS edge detection is performed by registering it in the IO flip flop with a global clock.The final data delay value therefore already accounts for the set up and hold times of the IO flip flops.Hence these parameteres are not considered in this analysis
Data hold time with respect to DQS         	0                    	0                 	0                 	
Clock jitter                               	150                     	150                          	150                          	Clock jitter that indirectly causes strobe jitter
Clock_tree_skew                            	25                  	25                         	25                         	Small value considered for skew on global clock line since detection of DQS and associated DQ are placed close to each other
Pcb_layout_skew                            	50                  	50                        	50                        	Skew between data lines and asociated strobe on the board
Uncertainities                             	1418.46                            	1020.00                         	1020.00                         	Total uncertainities
Window                                     	1343.46                           	1020.00                        	2363.46                        	Valid data window
Center of data valid window                	1691.73                 	                                        	                                        	
Number of taps in data valid window        	 16.79                 	                                        	                                        	
Pulse center or quarter period             	1879.70