xst.xmsgs

arm控制FPGA的DDR测试代码

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">write_cmd3</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">dqs_enable</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">dqs_reset</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">4</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">read_cmd5</arg>&gt; and currently occupies <arg fmt="%d" index="3">4</arg> logic cells (<arg fmt="%d" index="4">2</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">auto_ref</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">read_valid_data_1_r1</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">u_data_val</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">fifo_00_wr_addr_3d&lt;0&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">fifo_00_wr_addr_3d&lt;1&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">fifo_00_wr_addr_3d&lt;2&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">fifo_00_wr_addr_3d&lt;3&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">fifo_01_wr_addr_3d&lt;0&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">fifo_01_wr_addr_3d&lt;1&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">fifo_01_wr_addr_3d&lt;2&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">3</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">fifo_01_wr_addr_3d&lt;3&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">3</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">rst_calib1_r2</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">sys_rst_val</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">sys_rst90_val</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">sys_rst180_val</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">sys_rst270_val</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_32</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_33</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_34</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_35</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_36</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_37</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_38</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_39</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_40</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_41</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_42</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_43</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_44</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_45</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_46</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_47</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_48</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_49</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_50</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_51</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_52</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_53</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="1291" delta="unknown" >FF/Latch &lt;<arg fmt="%s" index="1">write_data270_54</arg>&gt; is unconnected in block &lt;<arg fmt="%s" index="2">ddr_cntl_a_data_write_0</arg>&gt;.
</msg>