xst.xmsgs

arm控制FPGA的DDR测试代码

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">reset180_r</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">ddr_casb5</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">column_address_reg6</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">config_reg&lt;9:7&gt;</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">config_reg&lt;3&gt;</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">DQS_enable4</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">row_address_conflict</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">read_enable_out_r</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">DQS_reset4_clk0</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">read_write_state</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">wrburst_end_8</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">wrburst_end_9</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">GND</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">ddr_rasb5</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">read_rcd_end</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">read_cmd_reg</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">ddr_web5</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">ddr_ba5</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">dly_dqs_div_r</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">ddr_address5</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">write_cmd</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">write_cmd8</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">command_reg</arg>&gt; is assigned but never used.
</msg>

<msg type="info" file="Xst" num="2117" delta="unknown" >HDL ADVISOR - Mux Selector &lt;<arg fmt="%s" index="1">next_state</arg>&gt; of Case statement line <arg fmt="%s" index="2">1101</arg> was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
	- add an &apos;<arg fmt="%s" index="3">INIT</arg>&apos; attribute on signal &lt;<arg fmt="%s" index="4">next_state</arg>&gt; (optimization is then done without any risk)
	- use the attribute &apos;<arg fmt="%s" index="5">signal_encoding</arg> <arg fmt="%s" index="6">user</arg>&apos; to avoid onehot optimization
	- use the attribute &apos;<arg fmt="%s" index="7">safe_implementation</arg> <arg fmt="%s" index="8">yes</arg>&apos; to force XST to perform a safe (but less efficient) optimization
</msg>

<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">auto_ref_req</arg>&gt; is never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">state</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">lfsr_data_m_r</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="647" delta="unknown" >Input &lt;<arg fmt="%s" index="1">SYS_CLKb</arg>&gt; is never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">vcc</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">data_valid_out1</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">delay_sel_tb</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">clk_out</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">clk90_out</arg>&gt; is assigned but never used.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">cnt_roll</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">burst_done</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">burst_length&lt;0&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">burst_length&lt;1&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">burst_length&lt;2&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">cas_latency&lt;0&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">cas_latency&lt;1&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">cas_latency&lt;2&gt;</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">AUTO_REF_detect</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>