nand01gr3b.vhd

nand flash NAND01GR3B (st)的仿真模型 （VHDL） 的

                         wait until AL'event and AL='0'; 
                    -- RandomDataInput or RandomDataOutput : get column address only and initialize nCycle     
                    elsif (Read_mode.mode=RandomDataInput_status or Read_mode.mode=RandomDataOutput_status) then
                         hold_address(ColumnAddress_range) <= hold_address_ext(ColumnAddress_range);
                         nCycle := 0; 
                         PrintString("[" & time2str(now) & "]  " &  chip_indication &
                                     "Column Address: " & slv2hex(hold_address_ext(ColumnAddress_range)) 
                                     & " (" & int2str(slv2int(hold_address_ext(ColumnAddress_range))) & ")" );
                    else
                         nCycle := nCycle + 1;
                    end if;   
                       

                  when 3 =>
                    
                    -- latch 3rd part of word address
                    hold_address_ext(18 downto 11) := I_O(7 downto 0);

                    -- latch 3rd part block address
                    if ( CD.size_dev = s_2G ) then 
                        hold_block_ext(10) := I_O(0);
                    elsif ( CD.size_dev = s_4G ) then     
                        hold_block_ext(11 downto 10) := I_O(1 downto 0);
                    elsif ( CD.size_dev = s_8G ) then    
                        hold_block_ext(12 downto 10) := I_O(2 downto 0);    
                    end if;

                    -- if size >= 2G , then block address is complete
                    if ( CD.size_dev >= s_2G ) then
                       hold_block <= hold_block_ext(BlockAddress_normRange);
                    end if;

                    -- when device is latching BlockAddress...                
                    if ( (CD.size_dev >= s_2G) and isLatchBlockAddress = true ) then
                         nCycle :=0;
                         PrintString("[" & time2str(now) & "]  " &  chip_indication &
                                      "Block Numer Latched: " &
                                      int2str(slv2int(hold_block_ext(BlockAddress_normRange))) );
                         isLatchBlockAddress := false;
                         --Kernel_LatchAddress <= now after 1 fs;
                         Kernel_LatchAddress <= now ;
                         wait until AL'event and AL='0';
                    else
                         nCycle := nCycle + 1;
                    end if;     


                  when 4 =>

                    -- latch 4rd part of word address
                    if ( CD.size_dev = s_512M ) then 
                        hold_address_ext(25 downto 19) := I_O(6 downto 0);
                    elsif ( CD.size_dev >= s_1G ) then
                        hold_address_ext(26 downto 19) := I_O(7 downto 0);
                    end if; 

                    -- if size <= 1G , then address is complete    
                    if ( CD.size_dev <= s_1G ) then
                        hold_address <= hold_address_ext(Address_range);
                        PrintString("[" & time2str(now) & "]  " &  chip_indication &
                                    "Address Input: " & slv2hex(hold_address_ext(Address_range)) &
                                    " (Block " & int2str(slv2int(hold_address_ext(BlockAddress_range))) 
                                    & ", Page " & int2str(slv2int(hold_address_ext(PageAddress_range)))
                                    & ", Column " & int2str(slv2int(hold_address_ext(ColumnAddress_range)))
                                    & ")");
                        nCycle := 0;
                    else
                        nCycle := nCycle + 1;
                    end if;    
                            
                            
                  when 5 =>

                    -- latch 5th part of word address
                    if ( CD.size_dev = s_2G ) then 
                        hold_address_ext(27) := I_O(0);
                    elsif ( CD.size_dev = s_4G ) then
                        hold_address_ext(28 downto 27) := I_O(1 downto 0);
                    elsif ( CD.size_dev = s_8G ) then
                        hold_address_ext(29 downto 27) := I_O(2 downto 0);    
                    end if;
                    
                    -- if size <= 8G , then address is complete    
                    if ( CD.size_dev <= s_8G ) then
                        hold_address <= hold_address_ext(Address_range);
                        PrintString("[" & time2str(now) & "]  " &  chip_indication &
                                    "Address Input: " & slv2hex(hold_address_ext(Address_range)) &
                                    " (Block " & int2str(slv2int(hold_address_ext(BlockAddress_range))) 
                                    & ", Page " & int2str(slv2int(hold_address_ext(PageAddress_range)))
                                    & ", Column " & int2str(slv2int(hold_address_ext(ColumnAddress_range)))
                                    & ")");
                        nCycle := 0;
                    end if;


                  when others => 
                
                       
                  end case;



              elsif (CD.bus_dev=bus8) then
              

                  case nCycle is


                  when 1 =>
                    hold_block_ext(1 downto 0) := I_O(7 downto 6);
                    hold_address_ext(7 downto 0)   := I_O(7 downto 0);
                    nCycle := nCycle + 1;


                  when 2 =>

                    -- latch 2nd part of word address
                    hold_address_ext(11 downto 8) := I_O(3 downto 0);
                    
                    -- latch 2nd part block address
                    if ( CD.size_dev = s_512M ) then 
                        hold_block_ext(8 downto 2) := I_O(6 downto 0);
                    else     
                        hold_block_ext(9 downto 2) := I_O(7 downto 0);
                    end if;
                    
                    -- if size = 512 or 1G then block address is complete
                    if ( CD.size_dev <= s_1G ) then
                       hold_block <= hold_block_ext(BlockAddress_normRange);
                    end if;    

                    -- control if column address is out of spare area
                    if (isLatchBlockAddress = false) and (I_O(3) = '1') then   
                        if slv2int(hold_address_ext(11 downto 0)) > PageSize - 1 then
                                 PrintString("[" & time2str(now) & "]  " &  chip_indication &
                                              "#Warning: Memory Address not valid in Spare Area: "
                                              & "Address[10 downto 6]=0 is assumend");
                                 hold_address_ext(10 downto 6) := (Others =>  '0');
                        end if;
                    end if;
                    
                    -- Copy Back operation: get column address for change Index Page in PageBuffer 
                    if (isCopyBackCmdCode and waitFirstCopyBackAddress = false) then 
                        hold_address(ColumnAddress_range) <= hold_address_ext(ColumnAddress_range);
                        nCycle := 0 ;
                        PrintString("[" & time2str(now) & "]  " &  chip_indication &
                                     "Column Address: " & slv2hex(hold_address_ext(ColumnAddress_range)) 
                                     & " (" & int2str(slv2int(hold_address_ext(ColumnAddress_range))) & ")" );
                    end if;

                    -- when device is latching BlockAddress...                
                    if ( (CD.size_dev <= s_1G) and isLatchBlockAddress = true ) then
                         nCycle :=0;
                         PrintString("[" & time2str(now) & "]  " &  chip_indication &
                                      "Block Number Latched: " &
                                      int2str(slv2int(hold_block_ext(BlockAddress_normRange))) );
                         isLatchBlockAddress := false;
                         Kernel_LatchAddress <= now ;
                         wait until AL'event and AL='0'; 
                    -- RandomDataInput or RandomDataOutput : get column address only and initialize nCycle     
                    elsif (Read_mode.mode=RandomDataInput_status or Read_mode.mode=RandomDataOutput_status) then
                         hold_address(ColumnAddress_range) <= hold_address_ext(ColumnAddress_range);
                         nCycle := 0; 
                         PrintString("[" & time2str(now) & "]  " &  chip_indication &
                                     "Column Address: " & slv2hex(hold_address_ext(ColumnAddress_range)) 
                                     & " (" & int2str(slv2int(hold_address_ext(ColumnAddress_range))) & ")" );
                    else
                         nCycle := nCycle + 1;
                    end if;   
                       

                  when 3 =>
                    
                    -- latch 3rd part of word address
                    hold_address_ext(19 downto 12) := I_O(7 downto 0);

                    -- latch 3rd part block address
                    if ( CD.size_dev = s_2G ) then 
                        hold_block_ext(10) := I_O(0);
                    elsif ( CD.size_dev = s_4G ) then     
                        hold_block_ext(11 downto 10) := I_O(1 downto 0);
                    elsif ( CD.size_dev = s_8G ) then    
                        hold_block_ext(12 downto 10) := I_O(2 downto 0);    
                    end if;

                    -- if size >= 2G , then block address is complete
                    if ( CD.size_dev >= s_2G ) then
                       hold_block <= hold_block_ext(BlockAddress_normRange);
                    end if;

                    -- when device is latching BlockAddress...                
                    if ( (CD.size_dev >= s_2G) and isLatchBlockAddress = true ) then
                         nCycle :=0;
                         PrintString("[" & time2str(now) & "]  " &  chip_indication &
                                      "Block Numer Latched: " &
                                      int2str(slv2int(hold_block_ext(BlockAddress_normRange))) );
                         isLatchBlockAddress := false;
                         Kernel_LatchAddress <= now ;
                         wait until AL'event and AL='0';
                    else
                         nCycle := nCycle + 1;
                    end if;     


                  when 4 =>

                    -- latch 4rd part of word address
                    if ( CD.size_dev = s_512M ) then 
                        hold_address_ext(26 downto 20) := I_O(6 downto 0);
                    elsif ( CD.size_dev >= s_1G ) then
                        hold_address_ext(27 downto 20) := I_O(7 downto 0);
                    end if; 

                    -- if size <= 1G , then address is complete    
                    if ( CD.size_dev <= s_1G ) then
                        hold_address <= hold_address_ext(Address_range);
                        PrintString("[" & time2str(now) & "]  " &  chip_indication &
                                    "Address Input: " & slv2hex(hold_address_ext(Address_range)) &
                                    " (Block " & int2str(slv2int(hold_address_ext(BlockAddress_range))) 
                                    & ", Page " & int2str(slv2int(hold_address_ext(PageAddress_range)))
                                    & ", Column " & int2str(slv2int(hold_address_ext(ColumnAddress_range)))
                                    & ")");
                        nCycle := 0;
                    else
                        nCycle := nCycle + 1;
                    end if;    
                            
                            
                  when 5 =>

                    -- latch 5th part of word address
                    if ( CD.size_dev = s_2G ) then 
                        hold_address_ext(28) := I_O(0);
                    elsif ( CD.size_dev = s_4G ) then
                        hold_address_ext(29 downto 28) := I_O(1 downto 0);
                    elsif ( CD.size_dev = s_8G ) then
                        hold_address_ext(30 downto 28) := I_O(2 downto 0);    
                    end if;
                    
                    -- if size <= 8G , then address is complete    
                    if ( CD.size_dev <= s_8G ) then
                        hold_address <= hold_address_ext(Address_range);
                        PrintString("[" & time2str(now) & "]  " &  chip_indication &
                                    "Address Input: " & slv2hex(hold_address_ext(Address_range)) &
                                    " (Block " & int2str(slv2int(hold_address_ext(BlockAddress_range))) 
                                    & ", Page " & int2str(slv2int(hold_address_ext(PageAddress_range)))
                                    & ", Column " & int2str(slv2int(hold_address_ext(ColumnAddress_range)))
                                    & ")");
                        nCycle := 0;
                    end if;


                  when others => 
                
                       
                  end case;          


              end if;



        end if;


     end if;

end if;


end process process_AddressLatch;








-- gestisce il bus di uscita richiamando l'entita' Output Buffer 

process_OutputEnableSetTiming : Process begin 

        wait until (RLE_N'event or reset'event); -- RLE_N <= R_N or CE_N or CL or AL or not(W_N)
        
        if (reset'event and not(reset)) then

                Buffer_task.task <= setDataZ;
                Buffer_task.putTime <= 0 ns;
        
        elsif (RLE_N'event and RLE_N='0') and (not(Kernel_Status.busy) or Read_mode.mode=readStatusReg_status) then  
        
                if (E_N_d1'event) then -- Bus Read Operation: E_N controlled
                    
                    Kernel_ReadEvent <= not (Kernel_ReadEvent);  
                    wait until kernel_ReadEventComplete'event;
                    Buffer_task.putTime <= tELQV(CD.TimeIndex_dev);
                    Buffer_task.task <= setDataValid;
                    Buffer_task.eventTime <= now;
                
                elsif (R_N_d1'event) then -- Bus Read Operation: R_N controlled
                
                    Kernel_ReadEvent <= not (Kernel_ReadEvent);  
                    wait until kernel_ReadEventComplete'event;
                    Buffer_task.putTime <= tRLQV(CD.TimeIndex_dev);
                    Buffer_task.task <= setDataValid;
                    Buffer_task.eventTime <= now;
                
                end if;
                    
        elsif (RLE_N'event and RLE_N='1') then

            if (E_N_d1'event) then  -- Bus Release controlled by E_N