test_wpn.vhd

nand flash NAND01GR3B (st)的仿真模型 （VHDL） 的

--   
--           _/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
--         _/                   _/  ____________________________________________ 
--         _/                  _/  /                                           / 
--         _/_/               _/  /                                NAND01GR3B / 
--          _/_/_/           _/  /                                           /  
--             _/_/         _/  /                                     1Gbit / 
--              _/_/       _/  /        8 bit, 2112 Byte Page, 1.8 V, NAND / 
--                _/      _/  /                                           / 
--                _/     _/  /                     VHDL Behavioral Model / 
--                _/    _/  /                               Version 3.0 / 
--             _/_/    _/  /                                           /
--          _/_/_/    _/  /     Copyright (c) 2006 STMicroelectronics / 
--        _/_/_/     _/  /___________________________________________/ 
--  _/_/_/_/_/      _/    
--  
--


------------------------------------------------------------------------------------------
--                     STIMULI OPERATIONS FOR NANDxB
--              
--                            
--                                                          ST Microelectronics
------------------------------------------------------------------------------------------




----------------------------------
--  LIBRARIES --------------------
----------------------------------

LIBRARY IEEE;
Use  IEEE.std_logic_1164.all;
LIBRARY work;
Use work.data.all;
Use work.TimingData.all;
Use work.UserData.all;
Use work.StringLib.all;

use ieee.std_logic_arith.all;






----------------------------------
---- ENTITY DECLARATION ----------
----------------------------------


Entity Stimuli is
port 
     (
      I_O : out IObus_type;
      E_N, R_N, W_N, WP_N, PRL : out std_logic;
      AL, CL: out std_logic;
      RB_N  : in   std_logic;
      Vss, Vdd: out real
     );
End Stimuli;






------------------------------------
------------------------------------
------------------------------------
--- ARCHITECTURE -------------------
------------------------------------
------------------------------------
------------------------------------





Architecture behavior of Stimuli is


-- signals for read signal generation 
signal CK : std_logic := '1';
signal read_cycle : boolean := false;

-- signals for address input
subtype hex_address is std_logic_vector(31 downto 0);
constant zero : std_logic_vector(7 downto 0) := (others => '0');
constant high_imp : IObus_type := (others => 'Z');

-- read signal period
constant PERIOD: time:= 60 ns; 
constant patt_len : integer := 20;






begin





-- Read signal generator
---- When read_cycle=true R_N toggle with T=PERIOD, starting
---- with 1 value; when read_cycle goes down R_N goes immediately
---- to 1
RN_toggle: process(CK, read_cycle) 
begin
   if read_cycle then 
     CK <= not CK after PERIOD/2;
   else 
     CK <= '1';
   end if;
end process;
R_N <= CK ;









-------------------------------
--  Stimuli generator ---------
-------------------------------


Main : process

-- variables for address input
variable A1, A2, A3, A4, A5: IObus_type;

-----------------------------------
-- Procedures used in the process
-----------------------------------

-- init device
procedure init is
begin
  if (CD.Vddmin_dev=Vddmin_R) then      Vdd <= 1.8;
  elsif (CD.Vddmin_dev=Vddmin_W) then   Vdd <= 3.0; 
  end if;
  E_N <='1';
  W_N <='1'; AL <='0'; CL <='0'; 
  WP_N <='1'; PRL <='0';
  I_O <= high_imp;  
  wait for 5000 ns;
  E_N <='0';
  wait for 100 ns;
end;
        
-- command input
procedure insert_command (D: in IObus_type_ext) is
variable D_int : IObus_type := D(IObus_range); 
begin
   I_O <= (others => 'Z'); wait for 5 ns;
   CL<='1'; W_N<='0';
   I_O <= D_int; wait for 25 ns;       
   W_N<='1'; wait for 10 ns;        
   CL<='0'; wait for 10 ns;
   I_O <= (others => 'Z'); wait for 10 ns;
end;

-- data input cycle
procedure insert_data (D: in IObus_type_ext) is
variable D_int : IObus_type := D(IObus_range);
begin
   I_O <= (others => 'Z'); wait for 5 ns;
   CL<='0'; W_N<='0';  
   I_O <= D_int ; wait for 25 ns;                   
   W_N<='1'; wait for 10 ns;                   
   I_O <= (others => 'Z'); wait for 10 ns;  
end;

-- incremental data pattern input 
procedure insert_pattern(length : in integer) is
begin
   for k in 1 to length loop
           I_O <= (others => 'Z'); wait for 10 ns;
           CL<='0'; W_N<='0';  
           I_O <= conv_std_logic_vector(k,IOBusWidth) ; wait for 30 ns;                   
           W_N<='1'; wait for 20 ns;                   
   end loop ; 
   I_O <= (others => 'Z'); wait for 10 ns;
end;

-- address input cycles 
procedure insert_address (A: in hex_address) is
begin
   
   if (CD.bus_dev=bus8) then
       A1 := A(7 downto 0);
       A2 := "0000" & A(11 downto 8);
       A3 := A(19 downto 12);
       if (CD.size_dev=s_512M) then     A4 := '0' & A(26 downto 20);       
       elsif (CD.size_dev=s_1G) then    A4 := A(27 downto 20);              
       elsif (CD.size_dev=s_2G) then    A4 := A(27 downto 20);      A5 := "0000000" & A(28);
       elsif (CD.size_dev=s_4G) then    A4 := A(27 downto 20);      A5 := "000000" & A(29 downto 28);
       elsif (CD.size_dev=s_8G) then    A4 := A(27 downto 20);      A5 := "00000" & A(30 downto 28);
       end if;
       
   elsif (CD.bus_dev=bus16) then
       A1 := zero &  A(7 downto 0);
       A2 := zero & "00000" & A(10 downto 8);
       A3 := zero & A(18 downto 11);
       if (CD.size_dev=s_512M) then     A4 := zero & '0' & A(25 downto 19);        
       elsif (CD.size_dev=s_1G) then    A4 := zero & A(26 downto 19);              
       elsif (CD.size_dev=s_2G) then    A4 := zero & A(26 downto 19);      A5 := zero & "0000000" & A(27);
       elsif (CD.size_dev=s_4G) then    A4 := zero & A(26 downto 19);      A5 := zero & "000000" & A(28 downto 27);
       elsif (CD.size_dev=s_8G) then    A4 := zero & A(26 downto 19);      A5 := zero & "00000" & A(29 downto 27);
       end if;
   end if;   
   
   CL <='0'; AL <='1'; wait for 5 ns;
   I_O <= high_imp; wait for 5 ns;
                           
   I_O <= A1; wait for 25 ns;
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;        
        
   I_O <= A2; wait for 25 ns; 
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;
                           
   I_O <= A3; wait for 25 ns;
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;

   I_O <= A4; wait for 25 ns;
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;

   if (CD.size_dev >= s_2G) then
       I_O <= A5; wait for 25 ns;
       W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;
   end if;
        
   I_O <= high_imp; wait for 15 ns; 
   AL<='0'; wait for 5 ns;       
end;


 -- two address cycle (column address)  
procedure insert_colAddress (A: in hex_address) is
begin

   if (CD.bus_dev=bus8) then
       A1 := A(7 downto 0);
       A2 := "0000" & A(11 downto 8);
   elsif (CD.bus_dev=bus16) then
       A1 := zero & A(7 downto 0);
       A2 := zero & "00000" & A(10 downto 8);
   end if;
   
   CL <='0'; AL <='1'; wait for 5 ns;
   I_O <= high_imp; wait for 5 ns;
                           
   I_O <= A1; wait for 25 ns;
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;        
        
   I_O <= A2; wait for 25 ns; 
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;

   I_O <= high_imp; wait for 15 ns; 
   AL<='0'; wait for 5 ns;
end;


 -- insert block address  
procedure insert_blockAddress (A: in hex_address) is
begin

   if (CD.bus_dev=bus8) then
       A3 := A(19 downto 12);
       if (CD.size_dev=s_512M) then     A4 := '0' & A(26 downto 20);       
       elsif (CD.size_dev=s_1G) then    A4 := A(27 downto 20);              
       elsif (CD.size_dev=s_2G) then    A4 := A(27 downto 20);      A5 := "0000000" & A(28);
       elsif (CD.size_dev=s_4G) then    A4 := A(27 downto 20);      A5 := "000000" & A(29 downto 28);
       elsif (CD.size_dev=s_8G) then    A4 := A(27 downto 20);      A5 := "00000" & A(30 downto 28);
       end if;       
   elsif (CD.bus_dev=bus16) then
       A3 := zero & A(18 downto 11);
       if (CD.size_dev=s_512M) then     A4 := zero & '0' & A(25 downto 19);        
       elsif (CD.size_dev=s_1G) then    A4 := zero & A(26 downto 19);              
       elsif (CD.size_dev=s_2G) then    A4 := zero & A(26 downto 19);      A5 := zero & "0000000" & A(27);
       elsif (CD.size_dev=s_4G) then    A4 := zero & A(26 downto 19);      A5 := zero & "000000" & A(28 downto 27);
       elsif (CD.size_dev=s_8G) then    A4 := zero & A(26 downto 19);      A5 := zero & "00000" & A(29 downto 27);
       end if;
   end if;

   CL <='0'; AL <='1'; wait for 5 ns;
   I_O <= high_imp; wait for 5 ns;
                           
   I_O <= A3; wait for 25 ns;
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;        
        
   I_O <= A4; wait for 25 ns; 
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;

   if (CD.size_dev >= s_2G) then
       I_O <= A5; wait for 25 ns;
       W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;
   end if;

   I_O <= high_imp; wait for 15 ns; 
   AL<='0'; wait for 5 ns;
end;   


-- bus read operation (n = number of memory location to be read)
procedure BusRead_op (n : in integer)  is
begin
   read_cycle <= true;
   wait for n*PERIOD ;    
   read_cycle <= false;
   wait for 100 ns;
end;

-- end stimuli
procedure end_stim is
begin
   E_N<='1';
   wait for 1000 ns;
   assert (false) report "End Of Stimuli" severity(warning);
   wait;
end;



-- addresses 
variable addr1 : hex_address := x"00060000"; 
variable addr2 : hex_address := x"00000000";


--------------------------------------------
--- Begin process for stimuli generation
--------------------------------------------


begin

  
init;


--*********************************
--******* PRL=0 *******************
--*********************************

--*                      **
--* Program when WP_N=1  **
--*                      **
-- program
insert_command(x"0080");
insert_address(addr1);
insert_pattern(patt_len);
insert_command(x"0010");
wait for PROGRAM_time;
-- read programmed data
insert_command(x"0000");
insert_address(addr1);
insert_command(x"0030");
wait for read_busy_time;
busRead_op(patt_len+2);
-- erase
insert_command(x"0060");
insert_blockAddress(addr1);
insert_command(x"00D0");
wait for erase_time;


--*                         **
--* Program when WP_N=0     **
--*                         **
-- set WP_N 0
WP_N <= '0'; wait for 0 ns;
-- program
insert_command(x"0080");
insert_address(addr1);
insert_pattern(patt_len);
insert_command(x"0010");
wait for PROGRAM_time;
-- read programmed data
insert_command(x"0000");
insert_address(addr1);
insert_command(x"0030");
wait for read_busy_time;
busRead_op(patt_len+2);






--*********************************
--******* PRL=1 *******************
--*********************************

printstring("");printstring("");printstring("");
PRL <= '1'; wait for 0 ns;
--*                      **
--* Program when WP_N=1  **
--*                      **
WP_N <= '1'; wait for 0 ns;
-- unlock block to be programmed
insert_command(x"0023");
insert_blockAddress(addr1);
insert_command(x"0024");
insert_blockAddress(addr1);
-- program
insert_command(x"0080");
insert_address(addr1);
insert_pattern(patt_len);
insert_command(x"0010");
wait for PROGRAM_time;
-- read programmed data
insert_command(x"0000");
insert_address(addr1);
insert_command(x"0030");
wait for read_busy_time;
busRead_op(patt_len+2);
-- erase
insert_command(x"0060");
insert_blockAddress(addr1);
insert_command(x"00D0");
wait for erase_time;


--*                         **
--* Program when WP_N=0     **
--*                         **
-- set WP_N 0
WP_N <= '0'; wait for 0 ns;
-- unlock block to be programmed
insert_command(x"0023");
insert_blockAddress(addr1);
insert_command(x"0024");
insert_blockAddress(addr1);
-- program
insert_command(x"0080");
insert_address(addr1);
insert_pattern(patt_len);
insert_command(x"0010");
wait for PROGRAM_time;
-- read programmed data
insert_command(x"0000");
insert_address(addr1);
insert_command(x"0030");
wait for read_busy_time;
busRead_op(patt_len+2);





--*********************************
--*** Lock status and WPN *********
--*********************************

printstring("");printstring("");printstring("");

-- WP_N=1 
WP_N <= '1'; wait for 10 ns;
-- unlock block 
insert_command(x"0023");
insert_blockAddress(addr1);
insert_command(x"0024");
insert_blockAddress(addr1);
-- WP_N=1 : read lock status
insert_command(x"007A");
insert_blockAddress(addr1);
BusRead_op(1);
insert_command(x"007A");
insert_blockAddress(addr2);
BusRead_op(1);
-- WP_N=0 (<100 ns)
WP_N <= '0'; wait for 10 ns;
-- WP_N=1 : read lock status again
WP_N <= '1'; wait for 10 ns;
insert_command(x"007A");
insert_blockAddress(addr1);
BusRead_op(1);
insert_command(x"007A");
insert_blockAddress(addr2);
BusRead_op(1);







-- end stimuli
end_stim;



end process;





end behavior;