cache_program.vhd

nand flash NAND01GR3B (st)的仿真模型 （VHDL） 的

--   
--           _/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
--         _/                   _/  ____________________________________________ 
--         _/                  _/  /                                           / 
--         _/_/               _/  /                                NAND01GR3B / 
--          _/_/_/           _/  /                                           /  
--             _/_/         _/  /                                     1Gbit / 
--              _/_/       _/  /        8 bit, 2112 Byte Page, 1.8 V, NAND / 
--                _/      _/  /                                           / 
--                _/     _/  /                     VHDL Behavioral Model / 
--                _/    _/  /                               Version 3.0 / 
--             _/_/    _/  /                                           /
--          _/_/_/    _/  /     Copyright (c) 2006 STMicroelectronics / 
--        _/_/_/     _/  /___________________________________________/ 
--  _/_/_/_/_/      _/    
--  
--
------------------------------------------------------------------------------------------
--                     STIMULI OPERATIONS FOR NANDx4B
--              
--                            
--                                                          ST Microelectronics
------------------------------------------------------------------------------------------




----------------------------------
--  LIBRARIES --------------------
----------------------------------

LIBRARY IEEE;
Use  IEEE.std_logic_1164.all;
LIBRARY work;
Use work.data.all;
Use work.TimingData.all;
Use work.UserData.all;

use ieee.std_logic_arith.all;
-- conv_std_logic_vector






----------------------------------
---- ENTITY DECLARATION ----------
----------------------------------


Entity Stimuli is
port 
     (
      I_O : out IObus_type;
      E_N, R_N, W_N, WP_N, PRL : out std_logic;
      AL, CL: out std_logic;
      RB_N  : in   std_logic;
      Vss, Vdd: out real
     );
End Stimuli;






------------------------------------
------------------------------------
------------------------------------
--- ARCHITECTURE -------------------
------------------------------------
------------------------------------
------------------------------------





Architecture behavior of Stimuli is


-- signals for read signal generation 
signal CK : std_logic := '1';
signal read_cycle : boolean := false;

-- signals for address input
subtype hex_address is std_logic_vector(31 downto 0);
constant zero : std_logic_vector(7 downto 0) := (others => '0');
constant high_imp : IObus_type := (others => 'Z');

-- read signal period
constant PERIOD: time:= 60 ns; 
--constant patt_len : integer := 20;






begin





-- Read signal generator
---- When read_cycle=true R_N toggle with T=PERIOD, starting
---- with 1 value; when read_cycle goes down R_N goes immediately
---- to 1
RN_toggle: process(CK, read_cycle) 
begin
   if read_cycle then 
     CK <= not CK after PERIOD/2;
   else 
     CK <= '1';
   end if;
end process;
R_N <= CK ;









-------------------------------
--  Stimuli generator ---------
-------------------------------


Main : process

-- variables for address input
variable A1, A2, A3, A4, A5: IObus_type;


-----------------------------------
-- Procedures used in the process
-----------------------------------

-- init device
procedure init is
begin
  if (CD.Vddmin_dev=Vddmin_R) then      Vdd <= 1.8;
  elsif (CD.Vddmin_dev=Vddmin_W) then   Vdd <= 3.0; 
  end if;
  E_N <='1';
  W_N <='1'; AL <='0'; CL <='0'; 
  WP_N <='1'; PRL <='1';
  I_O <= high_imp;  
  wait for 5000 ns;
  E_N <='0';
  wait for 100 ns;
end;
        
-- command input
procedure insert_command (D: in IObus_type_ext) is
variable D_int : IObus_type := D(IObus_range); 
begin
   I_O <= (others => 'Z'); wait for 5 ns;
   CL<='1'; W_N<='0';
   I_O <= D_int; wait for 25 ns;       
   W_N<='1'; wait for 10 ns;        
   CL<='0'; wait for 10 ns;
   I_O <= (others => 'Z'); wait for 10 ns;
end;

-- data input cycle
procedure insert_data (D: in IObus_type_ext) is
variable D_int : IObus_type := D(IObus_range);
begin
   I_O <= (others => 'Z'); wait for 5 ns;
   CL<='0'; W_N<='0';  
   I_O <= D_int ; wait for 25 ns;                   
   W_N<='1'; wait for 10 ns;                   
   I_O <= (others => 'Z'); wait for 10 ns;  
end;

-- incremental data pattern input 
procedure insert_pattern(length : in integer) is
begin
   for k in 1 to length loop
           I_O <= (others => 'Z'); wait for 10 ns;
           CL<='0'; W_N<='0';  
           I_O <= conv_std_logic_vector(k,IOBusWidth) ; wait for 30 ns;                   
           W_N<='1'; wait for 20 ns;                   
   end loop ; 
   I_O <= (others => 'Z'); wait for 10 ns;
end;

-- address input cycles 
procedure insert_address (A: in hex_address) is
begin
   
   if (CD.bus_dev=bus8) then
       A1 := A(7 downto 0);
       A2 := "0000" & A(11 downto 8);
       A3 := A(19 downto 12);
       if (CD.size_dev=s_512M) then     A4 := '0' & A(26 downto 20);       
       elsif (CD.size_dev=s_1G) then    A4 := A(27 downto 20);              
       elsif (CD.size_dev=s_2G) then    A4 := A(27 downto 20);      A5 := "0000000" & A(28);
       elsif (CD.size_dev=s_4G) then    A4 := A(27 downto 20);      A5 := "000000" & A(29 downto 28);
       elsif (CD.size_dev=s_8G) then    A4 := A(27 downto 20);      A5 := "00000" & A(30 downto 28);
       end if;
       
   elsif (CD.bus_dev=bus16) then
       A1 := zero &  A(7 downto 0);
       A2 := zero & "00000" & A(10 downto 8);
       A3 := zero & A(18 downto 11);
       if (CD.size_dev=s_512M) then     A4 := zero & '0' & A(25 downto 19);        
       elsif (CD.size_dev=s_1G) then    A4 := zero & A(26 downto 19);              
       elsif (CD.size_dev=s_2G) then    A4 := zero & A(26 downto 19);      A5 := zero & "0000000" & A(27);
       elsif (CD.size_dev=s_4G) then    A4 := zero & A(26 downto 19);      A5 := zero & "000000" & A(28 downto 27);
       elsif (CD.size_dev=s_8G) then    A4 := zero & A(26 downto 19);      A5 := zero & "00000" & A(29 downto 27);
       end if;
   end if;   
   
   CL <='0'; AL <='1'; wait for 5 ns;
   I_O <= high_imp; wait for 5 ns;
                           
   I_O <= A1; wait for 25 ns;
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;        
        
   I_O <= A2; wait for 25 ns; 
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;
                           
   I_O <= A3; wait for 25 ns;
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;

   I_O <= A4; wait for 25 ns;
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;

   if (CD.size_dev >= s_2G) then
       I_O <= A5; wait for 25 ns;
       W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;
   end if;
        
   I_O <= high_imp; wait for 15 ns; 
   AL<='0'; wait for 5 ns;       
end;


 -- two address cycle (column address)  
procedure insert_colAddress (A: in hex_address) is
begin

   if (CD.bus_dev=bus8) then
       A1 := A(7 downto 0);
       A2 := "0000" & A(11 downto 8);
   elsif (CD.bus_dev=bus16) then
       A1 := zero & A(7 downto 0);
       A2 := zero & "00000" & A(10 downto 8);
   end if;
   
   CL <='0'; AL <='1'; wait for 5 ns;
   I_O <= high_imp; wait for 5 ns;
                           
   I_O <= A1; wait for 25 ns;
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;        
        
   I_O <= A2; wait for 25 ns; 
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;

   I_O <= high_imp; wait for 15 ns; 
   AL<='0'; wait for 5 ns;
end;


 -- insert block address  
procedure insert_blockAddress (A: in hex_address) is
begin

   if (CD.bus_dev=bus8) then
       A3 := A(19 downto 12);
       if (CD.size_dev=s_512M) then     A4 := '0' & A(26 downto 20);       
       elsif (CD.size_dev=s_1G) then    A4 := A(27 downto 20);              
       elsif (CD.size_dev=s_2G) then    A4 := A(27 downto 20);      A5 := "0000000" & A(28);
       elsif (CD.size_dev=s_4G) then    A4 := A(27 downto 20);      A5 := "000000" & A(29 downto 28);
       elsif (CD.size_dev=s_8G) then    A4 := A(27 downto 20);      A5 := "00000" & A(30 downto 28);
       end if;       
   elsif (CD.bus_dev=bus16) then
       A3 := zero & A(18 downto 11);
       if (CD.size_dev=s_512M) then     A4 := zero & '0' & A(25 downto 19);        
       elsif (CD.size_dev=s_1G) then    A4 := zero & A(26 downto 19);              
       elsif (CD.size_dev=s_2G) then    A4 := zero & A(26 downto 19);      A5 := zero & "0000000" & A(27);
       elsif (CD.size_dev=s_4G) then    A4 := zero & A(26 downto 19);      A5 := zero & "000000" & A(28 downto 27);
       elsif (CD.size_dev=s_8G) then    A4 := zero & A(26 downto 19);      A5 := zero & "00000" & A(29 downto 27);
       end if;
   end if;

   CL <='0'; AL <='1'; wait for 5 ns;
   I_O <= high_imp; wait for 5 ns;
                           
   I_O <= A3; wait for 25 ns;
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;        
        
   I_O <= A4; wait for 25 ns; 
   W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;

   if (CD.size_dev >= s_2G) then
       I_O <= A5; wait for 25 ns;
       W_N<='0'; wait for 25 ns; W_N<='1'; wait for 10 ns;
   end if;

   I_O <= high_imp; wait for 15 ns; 
   AL<='0'; wait for 5 ns;
end;   


-- bus read operation (n = number of memory location to be read)
procedure BusRead_op (n : in integer)  is
begin
   read_cycle <= true;
   wait for n*PERIOD ;    
   read_cycle <= false;
   wait for 100 ns;
end;

-- end stimuli
procedure end_stim is
begin
   E_N<='1';
   wait for 1000 ns;
   assert (false) report "End Of Stimuli" severity(warning);
   wait;
end;



-- address to be programmed
variable addr1, addr2, addr3, addr4 : hex_address ; 





--------------------------------------------
--- Begin process for stimuli generation
--------------------------------------------


begin


   if (CD.bus_dev=bus16) then
     addr1 := x"0001FC1F"; -- block 0 / last page / last column of spare area
     addr2 := x"00020000"; -- block 1 / first page
     addr3 := x"00020800"; -- block 1 / second page
     addr4 := x"00021000"; -- block 1 / third page
   elsif (CD.bus_dev=bus8) then
     addr1 := x"0003F83F";
     addr2 := x"00040000";
     addr3 := x"00041000";
     addr4 := x"00042000";
   end if;
  
  
   init;

 
-- Block unlock

  insert_command (X"0023");  
  wait for 100 ns;

  insert_blockAddress (x"00000000");  -- block 0 
  wait for 100 ns;
       
  insert_command (X"0024");
  
  insert_blockAddress (addr2);   -- block 1   
  wait for 100 ns;
       
       
       

-- Cache program 1 : block 0 / last page  

  insert_command (X"0080");
  wait for 100 ns;
  
  insert_address (addr1);                
  wait for 50 ns;
       
  insert_data (X"0013");                                 
  wait for 50 ns ;
       
  insert_command (X"0015");
  wait for 50 ns ;


-- Try to read afer CacheBusy state, but before busy state

  wait for CACHE_time ;

  insert_command (X"0000");
  insert_address (addr1);               
  insert_command (X"0030");

  
-- Cache program 2 : block 1 / first page 

  
  insert_command (X"0080");
  wait for 100 ns;
  
  insert_address (addr2);                
  wait for 50 ns;
       
  insert_data ( X"0013" );                                 
  wait for 50 ns ;
       
  insert_command (X"0015");
  wait for 50 ns ;

    

-- Cache program 3 : block 1 / second page
-- try before device exit busy state

  wait for CACHE_time;

  insert_command (X"0080");
  wait for 100 ns;
  
  insert_address (addr3);                
  wait for 50 ns;
       
  insert_data ( X"0013" );                                 
  wait for 50 ns ;
       
  insert_command (X"0015");
  wait for 50 ns ;
  
 
  

-- Cache program 3 : block 1 / second page
-- after device exit busy state

  wait for 2*PROGRAM_time  ;
  
  insert_command (X"0080");
  wait for 100 ns;
  
  insert_address (addr3);                
  wait for 50 ns;
       
  insert_data ( X"0013" );                                 
  wait for 50 ns ;
       
  insert_command (X"0015");
  wait for 50 ns ;



-- Program 4 (exit cache program mode) : block 1 / third page
-- after device exit busy state

  wait for PROGRAM_time  ;
  
  insert_command (X"0080");
  wait for 100 ns;
  
  insert_address (addr4);                
  wait for 50 ns;
       
  insert_data ( X"0013" );                                 
  wait for 50 ns ;
       
  insert_command (X"0010");
  wait for 50 ns ;


 
-- Read 1

  wait for PROGRAM_time  + 2*CACHE_time  ;

  insert_command (X"0000");
  insert_address (addr1);               
  insert_command (X"0030");
  wait for 100 ns;
  wait for READ_BUSY_time;

  BusRead_op(1);
  wait for 100 ns;


-- Read 2     

  insert_address (addr2);               
  insert_command (X"0030");
  wait for 100 ns;
  wait for READ_BUSY_time;

  BusRead_op(1);
  wait for 100 ns;


-- Read 3     

  insert_address (addr3);               
  insert_command (X"0030");
  wait for 100 ns;
  wait for READ_BUSY_time;

  BusRead_op(1);
  wait for 100 ns;



-- Read 4     

  insert_address (addr4);               
  insert_command (X"0030");
  wait for 100 ns;
  wait for READ_BUSY_time;

  BusRead_op(1);
  wait for 100 ns;  


-- end stimuli

  end_stim;





end process;





end behavior;