testbench.vhd

nand flash NAND01GR3B (st)的仿真模型 （VHDL） 的

--   
--           _/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
--         _/                   _/  ____________________________________________ 
--         _/                  _/  /                                           / 
--         _/_/               _/  /                                NAND01GR3B / 
--          _/_/_/           _/  /                                           /  
--             _/_/         _/  /                                     1Gbit / 
--              _/_/       _/  /        8 bit, 2112 Byte Page, 1.8 V, NAND / 
--                _/      _/  /                                           / 
--                _/     _/  /                     VHDL Behavioral Model / 
--                _/    _/  /                               Version 3.0 / 
--             _/_/    _/  /                                           /
--          _/_/_/    _/  /     Copyright (c) 2006 STMicroelectronics / 
--        _/_/_/     _/  /___________________________________________/ 
--  _/_/_/_/_/      _/    
--  
--


LIBRARY IEEE;
    Use IEEE.std_logic_1164.all;

LIBRARY Work;
    Use work.UserData.all;
    Use work.data.all;


----------------------------
------  Entity Top  --------
----------------------------

entity Top is
  begin
end Top;



------------------------------
-----  Top Architecture  -----
------------------------------

architecture TestBench of top is


Component stimuli
port 
      (
      I_O  : out IObus_type;
      
      E_N : out std_logic;
      R_N  : out std_logic;
      W_N  : out std_logic;
      WP_N : out std_logic;
      AL   : out std_logic;
      CL   : out std_logic;
      PRL  : out std_logic;
      RB_N: in   std_logic;
      
      Vss  : out real;
      Vdd  : out real
      );
      
end component;

Component NANDxxxxxBx
  GENERIC (     devId               : natural;
                isDebug             : boolean;
                MemoryFile_Name     : String;
                timingCheck_on      : Boolean  );
  PORT  (
      I_O    : inout IObus_type;
      E_N   : in std_logic;
      R_N    : in std_logic;
      W_N    : in std_logic;
      AL     : in std_logic;
      CL     : in std_logic;
      WP_N   : in std_logic;
      PRL    : in std_logic;
      RB_N  : out std_logic;
      Vss    : in real;
      Vdd    : in real
  );
end component;


signal  I_O  : IObus_type;
signal  E_N, R_N, W_N, WP_N,  PRL  : std_logic;
signal  AL, CL : std_logic;
signal  RB_N : std_logic;
signal  Vss, Vdd : real;     
 



begin

stim    : stimuli port map
                 (
                  I_O   => I_O, 
                  E_N  => E_N, 
                  R_N   => R_N, 
                  W_N   => W_N, 
                  WP_N  => WP_N,
                  AL  => AL,
                  CL  => CL,
                  PRL => PRL,
                  RB_N => RB_N,
                  Vss   => Vss,
                  Vdd   => Vdd 
                  );

DUT     : NANDxxxxxBx
		generic map ( 0, isDebug , memory_file , timingCheck_on )
                port map
                 (
                 I_O   => I_O, 
                 E_N  => E_N,
                 R_N   => R_N, 
                 W_N   => W_N, 
                 WP_N  => WP_N,
                 AL  => AL,
                 CL  => CL,
                 PRL => PRL,
                 RB_N  => RB_N,
                 Vss   => Vss,
                 Vdd   => Vdd 
                 );

end TestBench;