📄 timingdata.vhd
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-- -- _/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/-- _/ _/ ____________________________________________ -- _/ _/ / / -- _/_/ _/ / NAND01GR3B / -- _/_/_/ _/ / / -- _/_/ _/ / 1Gbit / -- _/_/ _/ / 8 bit, 2112 Byte Page, 1.8 V, NAND / -- _/ _/ / / -- _/ _/ / VHDL Behavioral Model / -- _/ _/ / Version 3.0 / -- _/_/ _/ / /-- _/_/_/ _/ / Copyright (c) 2006 STMicroelectronics / -- _/_/_/ _/ /___________________________________________/ -- _/_/_/_/_/ _/ -- --LIBRARY IEEE;Use IEEE.std_logic_1164.all;LIBRARY Work;Use Work.data.all;package TimingData is type timings is array(version) of time;------------------------------------------------------------------------------------------------ Timing data --- ----- from datasheet: --- ----- * F90 : NAND01G-B, NAND02G-B (February 2006 - Rev 4) -------- * F70_R, F70_W : NAND01G-B2B, NAND02G-B2C (June 2006 - Rev 2) (no PRL) -------- * F70_2W : NAND04GW3B2B, NAND08GW3B2A (May 2006 - Rev 2)(PRL) ---------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- AC Characteristics for Command, Address, Data Input ---------------------------------------------------------------------------------------------------------------- only F70 ; in F90 WH replaced by WL (check implemented directly in TimingCheck.vhd)--******************************* F90_R F90_W F70_R F70_W F70_2R F70_2Wconstant tALLWH : timings := ( 0 ns, 0 ns, 25 ns, 15 ns, 0 ns, 15 ns ); -- Address Latch Low to Write Enable Lowconstant tALHWH : timings := ( 0 ns, 0 ns, 25 ns, 15 ns, 0 ns, 15 ns ); -- Address Latch High to Write Enable Highconstant tCLHWH : timings := ( 0 ns, 0 ns, 25 ns, 15 ns, 0 ns, 15 ns ); -- Command Latch High to Write Enable Highconstant tCLLWH : timings := ( 0 ns, 0 ns, 25 ns, 15 ns, 0 ns, 15 ns ); -- Command Latch Low to Write Enable Highconstant tELWH : timings := ( 0 ns, 0 ns, 35 ns, 20 ns, 0 ns, 25 ns ); -- Chip Enable Low to Write Enable High--******************************* F90_R F90_W F70_R F70_W F70_2R F70_2Wconstant tDVWH : timings := ( 20 ns, 20 ns, 20 ns, 15 ns, 0 ns, 15 ns ); -- Data Valid to Write Enable Highconstant tWHALH : timings := ( 10 ns, 10 ns, 10 ns, 5 ns, 0 ns, 5 ns ); -- Write Enable High to Address Latch Highconstant tWHCLH : timings := ( 10 ns, 10 ns, 10 ns, 5 ns, 0 ns, 5 ns ); -- Write Enable High to Command Latch Highconstant tWHCLL : timings := ( 10 ns, 10 ns, 10 ns, 5 ns, 0 ns, 5 ns ); -- Write Enable High to Command Latch Low constant tWHDX : timings := ( 10 ns, 10 ns, 10 ns, 5 ns, 0 ns, 5 ns ); -- Write Enable High to Data Transitionconstant tWHEH : timings := ( 10 ns, 10 ns, 10 ns, 5 ns, 0 ns, 5 ns ); -- Write Enable High to Chip Enable Highconstant tWHWL : timings := ( 20 ns, 20 ns, 15 ns, 10 ns, 0 ns, 10 ns ); -- Write Enable High to Write Enable Lowconstant tWLWH : timings := ( 25 ns, 25 ns, 25 ns, 15 ns, 0 ns, 20 ns ); -- Write Enable Low to Write Enable Highconstant tWLWH_2 : timings := ( 35 ns, 35 ns, 0 ns, 0 ns, 0 ns, 0 ns ); -- Write Enable Low to Write Enable High (when tELWL < 10 ns - only F90) constant tWLWL : timings := ( 60 ns, 50 ns, 45 ns, 30 ns, 0 ns, 35 ns ); -- Write Enable Low to Write Enable Low --------------------------------------------------------------------------------- AC Characteristics for Operations ----------------------------------------------------------------------------------------------******************************* F90_R F90_W F70_R F70_W F70_2R F70_2Wconstant tALLRL1 : timings := ( 10 ns, 10 ns, 10 ns, 10 ns, 0 ns, 15 ns ); -- Address Latch Low to Read Enable Low - Read Electronic Signatureconstant tALLRL2 : timings := ( 10 ns, 10 ns, 10 ns, 10 ns, 0 ns, 15 ns ); -- Address Latch Low to Read Enable Low - Read Cycleconstant tBHRL : timings := ( 20 ns, 20 ns, 20 ns, 20 ns, 0 ns, 20 ns ); -- Ready/Busy High to Read Enable Lowconstant tBLBH1 : timings := ( 25 us, 25 us, 25 us, 25 us, 0 us, 25 us ); -- Ready/Busy Low to Ready/Busy High - Read Busy timeconstant tBLBH2 : timings := ( 700 us, 700 us, 700 us, 700 us, 0 us, 700 us ); -- Ready/Busy Low to Ready/Busy High - Program Busy timeconstant tBLBH3 : timings := ( 3 ms, 3 ms, 3 ms, 3 ms, 0 ms, 3 ms ); -- Ready/Busy Low to Ready/Busy High - Erase Busy timeconstant tBLBH4 : timings := ( 5 us, 5 us, 5 us, 5 us, 0 us, 5 us ); -- Ready/Busy Low to Ready/Busy High - Reset Busy time, during readyconstant tBLBH5 : timings := ( 3 us, 3 us, 3 us, 3 us, 0 us, 3 us ); -- Ready/Busy Low to Ready/Busy High - Cache Busy timeconstant tWHBH1_1 : timings := ( 5 us, 5 us, 5 us, 5 us, 0 us, 5 us ); -- Write Enable High to Ready/Busy High - Reset Busy time, during read constant tWHBH1_2 : timings := ( 10 us, 10 us, 10 us, 10 us, 0 us, 10 us ); -- Write Enable High to Ready/Busy High - Reset Busy time, during program constant tWHBH1_3 : timings := ( 500 us, 500 us, 500 us, 500 us, 0 us, 500 us ); -- Write Enable High to Ready/Busy High - Reset Busy time, during erase constant tCLLRL : timings := ( 10 ns, 10 ns, 10 ns, 10 ns, 0 ns, 15 ns ); -- Command Latch Low to Read Enable Lowconstant tDZRL : timings := ( 0 ns, 0 ns, 0 ns, 0 ns, 0 ns, 0 ns ); -- Data Hi-Z to Read Enable Lowconstant tEHQZ : timings := ( 20 ns, 20 ns, 30 ns, 30 ns, 0 ns, 50 ns ); -- Chip Enable High to Output Hi-Z constant tRHQZ : timings := ( 30 ns, 30 ns, 30 ns, 30 ns, 0 ns, 50 ns ); -- Read Enable High to Output Hi-Zconstant tELQV : timings := ( 45 ns, 45 ns, 45 ns, 25 ns, 0 ns, 30 ns ); -- Chip Enable Low to Output Validconstant tRHRL : timings := ( 20 ns, 20 ns, 15 ns, 10 ns, 0 ns, 10 ns ); -- Read Enable High to Read Enable Low constant tEHQX : timings := ( 15 ns, 15 ns, 10 ns, 10 ns, 0 ns, 15 ns ); -- Chip Enable High to Output Hold constant tRHQX : timings := ( 15 ns, 15 ns, 10 ns, 10 ns, 0 ns, 15 ns ); -- Read Enable High to Output Holdconstant tRLRH : timings := ( 25 ns, 25 ns, 25 ns, 15 ns, 0 ns, 15 ns ); -- Read Enable Low to Read Enable Highconstant tRLRL : timings := ( 60 ns, 50 ns, 50 ns, 30 ns, 0 ns, 30 ns ); -- Read Enable Low to Read Enable Lowconstant tRLQV : timings := ( 35 ns, 35 ns, 30 ns, 20 ns, 0 ns, 25 ns ); -- Read Enable Low to Output Validconstant tWHBH : timings := ( 25 us, 25 us, 25 us, 25 us, 0 us, 25 us ); -- Write Enable High to Ready/Busy High constant tWHBL : timings := ( 100 ns, 100 ns, 100 ns, 100 ns, 0 ns, 100 ns ); -- Write Enable High to Ready/Busy Lowconstant tWHRL : timings := ( 60 ns, 60 ns, 60 ns, 60 ns, 0 ns, 60 ns ); -- Write Enable High to Read Enable Low-- F70 only--******************************* F90_R F90_W F70_R F70_W F70_2R F70_2Wconstant tRHRL2 : timings := ( 0 ns, 0 ns, 50 ns, 50 ns, 0 ns, 100 ns ); -- Read Enable High hold time during Cache Read operationconstant tWHWH : timings := ( 0 ns, 0 ns, 100 ns, 100 ns, 0 ns, 100 ns ); -- Last Address Latched to Data Loading constant tWW : timings := ( 0 ns, 0 ns, 100 ns, 100 ns, 0 ns, 100 ns ); -- WP_N transition to W_N high------------------------------------------- Alias used in VHDL code -------------------------------------------------------Constant CACHE_time : time := tBLBH5(CD.TimeIndex_dev)+tWHBL(CD.TimeIndex_dev);Constant RB_delay : time := tWHBL(CD.TimeIndex_dev);------------------------------------------------------------------------------------------ ======== User Can Redefine Following Constants For Reduce Simulation Time ======== ------------------------------------------------------------------------------------------Constant READ_BUSY_time : time := tBLBH1(CD.TimeIndex_dev)+RB_delay;Constant PROGRAM_time : time := tBLBH2(CD.TimeIndex_dev)+RB_delay;Constant ERASE_time : time := tBLBH3(CD.TimeIndex_dev)+RB_delay;Constant RESET_time : time := tBLBH4(CD.TimeIndex_dev)+RB_delay; end;⌨️ 快捷键说明
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