leg_dcache.v

verilog hdl编写,六段流水线CPU.程序完整

//keep the input address 
always@(posedge clk or posedge rst)
begin
        if (rst) begin
                d_addr_d <= 32'h0;
        end
        else begin
                if (!d_wait && (d_re || d_we))
                        d_addr_d <= d_address; 
        end
end

//keep one cycle of we
always@(posedge clk or posedge rst)
begin
        if (rst) begin
                d_we_d <= 1'b0;
        end
        else begin
                if (!d_wait)
                        d_we_d <= d_we; 
        end
end

always@(posedge clk or posedge rst)
begin
        if (rst) begin
                d_re_d <= 1'b0;
        end
        else begin
                if (!d_wait)
                        d_re_d <= d_re; 
        end
end

//keep one cycle of be
always@(posedge clk or posedge rst)
begin
        if (rst) begin
                d_be_d <= 4'h0;
        end
        else begin
                if (!d_wait)
                        d_be_d <= d_be; 
        end
end

//decode the cache line addr
always@(posedge clk or posedge rst)
begin
        if (rst) begin
                write_word_decode <= 4'b0000;
        end
        else begin
                if (!d_wait)
                        case(d_address[3:2])
                        2'b00: write_word_decode <= 4'b0001;
                        2'b01: write_word_decode <= 4'b0010;
                        2'b10: write_word_decode <= 4'b0100;
                        2'b11: write_word_decode <= 4'b1000;
                        endcase
        end
end

//d cache fsm
//this fsm only process the read operation

always@(posedge clk or posedge rst)
begin
        if (rst) begin
                d_cache_state <= IDLE;
                send_counter <= 2'b00;
                receive_counter <= 2'b00;     
                mem_read <= 1'b0;           
        end
        else begin
                case(d_cache_state)
                IDLE: begin
                        if (d_re) begin
                                d_cache_state <= HIT_DETECT;
                        end
                end
                HIT_DETECT: begin
                        if (!d_tag_read_hit && d_read_d) begin       //hit miss
                                d_cache_state <= RELOAD_1;
                                mem_read <= 1'b1;
                                send_counter <= 2'b00;
                                receive_counter <= 2'b00;
                        end
                end
                RELOAD_1: begin
                        //send 4 memory request, burst
                        //if not get responce, then wait
                        
                        if (send_counter == 2'b11) begin
                                d_cache_state <= RELOAD_2;
                                mem_read <= 1'b0;
                        end
                        else
                                send_counter <= send_counter + 2'b01;
                        //get received data, if can
                        if (receive_valid)
                                receive_counter <= receive_counter + 2'b01;
                end
                RELOAD_2: begin
                        if (receive_counter == 2'b11) begin
                                d_cache_state <= HIT_DETECT;
                                send_counter <= 2'b00;
                                receive_counter <= 2'b00;
                        end
                        else if (receive_valid)
                                receive_counter <= receive_counter + 2'b01;
                end
                //other case
                default: begin
                        d_cache_state <= IDLE;
                        send_counter <= 2'b00;
                        receive_counter <= 2'b00;     
                        mem_read <= 1'b0;  
                end
                endcase
        end
end
//--------------------------------------------------------------------
//memory instances
//data cache are divided into 4 bank in order to read/write individually
//cache memory instance 0
leg_dpram_syn   d_cache_mem_0(
                        .raddr(d_cache_mem_raddr),
                        .rdata(d_cache_mem_rdata[31:24]),
                        .waddr(d_cache_mem_waddr),
                        .wdata(d_cache_mem_wdata[31:24]),
                        .re(1'b1),
                        .we(d_cache_mem_we[3]),
                        .clk(clk),
                        .rst(rst)
                        );
defparam        d_cache_mem_0.AW = 10;    //1024 BYTE, TOTAL 1K BYTES, 2 m4k
defparam        d_cache_mem_0.DW = 8;    //32 bit inst

//cache memory instance 1
leg_dpram_syn   d_cache_mem_1(
                        .raddr(d_cache_mem_raddr),
                        .rdata(d_cache_mem_rdata[23:16]),
                        .waddr(d_cache_mem_waddr),
                        .wdata(d_cache_mem_wdata[23:16]),
                        .re(1'b1),
                        .we(d_cache_mem_we[2]),
                        .clk(clk),
                        .rst(rst)
                        );
defparam        d_cache_mem_1.AW = 10;    //1024 BYTE, TOTAL 1K BYTES, 2 m4k
defparam        d_cache_mem_1.DW = 8;    //32 bit inst

//cache memory instance 2
leg_dpram_syn   d_cache_mem_2(
                        .raddr(d_cache_mem_raddr),
                        .rdata(d_cache_mem_rdata[15:08]),
                        .waddr(d_cache_mem_waddr),
                        .wdata(d_cache_mem_wdata[15:08]),
                        .re(1'b1),
                        .we(d_cache_mem_we[1]),
                        .clk(clk),
                        .rst(rst)
                        );
defparam        d_cache_mem_2.AW = 10;    //1024 BYTE, TOTAL 1K BYTES, 2 m4k
defparam        d_cache_mem_2.DW = 8;    //32 bit inst

//cache memory instance 3
leg_dpram_syn   d_cache_mem_3(
                        .raddr(d_cache_mem_raddr),
                        .rdata(d_cache_mem_rdata[07:00]),
                        .waddr(d_cache_mem_waddr),
                        .wdata(d_cache_mem_wdata[07:00]),
                        .re(1'b1),
                        .we(d_cache_mem_we[0]),
                        .clk(clk),
                        .rst(rst)
                        );
defparam        d_cache_mem_3.AW = 10;    //1024 BYTE, TOTAL 1K BYTES, 2 m4k
defparam        d_cache_mem_3.DW = 8;    //32 bit inst

//cache tag instance
//no flag at this simple implementation
leg_dpram_syn   d_cache_tag(
                        .raddr(d_cache_tag_raddr),
                        .rdata(d_cache_tag_rdata),
                        .waddr(d_cache_tag_waddr),
                        .wdata(d_cache_tag_wdata),
                        .re(1'b1),
                        .we(d_cache_tag_we),
                        .clk(clk),
                        .rst(rst)
                        );
defparam        d_cache_tag.AW = 8;     //256 WORD, TOTAL 512 ENTRY
defparam        d_cache_tag.DW = 24;    //20 bit, total 2 m4k



endmodule