_primary.vhd

来自「verilog hdl编写,六段流水线CPU.程序完整」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity leg_shifter is
    port(
        din             : in     vl_logic_vector(31 downto 0);
        dout            : out    vl_logic_vector(31 downto 0);
        shift_oprand    : in     vl_logic_vector(4 downto 0);
        direction       : in     vl_logic;
        mode            : in     vl_logic_vector(2 downto 0);
        carry_in        : in     vl_logic;
        carry_out       : out    vl_logic
    );
end leg_shifter;