pwm.v

用硬件描述语言实现的灯控IP核

module pwm
(   
   clk,
   resetn,
   write,
   chipselect,
   wdata,
   red_out,
   green_out,
   blue_out
);

//avalon_slave_pwm avalon I/O
input clk;
input write;
input resetn;
input chipselect;
input [31:0] wdata;

//avalon_slave_pwm exported I/O
output red_out;
output green_out;
output blue_out;

//avalon_slave_pwm interal nodes
reg[7:0] red_duty_in;
reg[7:0] green_duty_in;
reg[7:0] blue_duty_in;




reg[7:0] red_duty_out;
reg[7:0] green_duty_out;
reg[7:0] blue_duty_out;

reg[8:0] counter256;
reg[9:0] counter664;

reg red_out;
reg green_out;
reg blue_out;



//assign data0[23:16]=writedata[7:5]*36;
//assign data0[15:8]=writedata[4:2]*36;
//assign data0[7:0]=writedata[1:0]*85;



always@(posedge clk or negedge resetn)
begin
  if(~resetn)
    begin
    counter256[8:0]=9'b000000000;
    counter664[9:0]=10'b0000000000;
    red_duty_out[7:0]=8'b00000000;
    green_duty_out[7:0]=8'b00000000;
    blue_duty_out[7:0]=8'b00000000;
    end
   else if(counter664[9:0]==663)
       begin
           counter664[9:0]=10'b0000000000;
           if(counter256[8:0]==255)
             begin
               counter256[8:0]=9'b000000000;
               red_duty_out[7:0]=red_duty_in[7:0];
               green_duty_out[7:0]=green_duty_in[7:0];
               blue_duty_out[7:0]=blue_duty_in[7:0];
             end
           else
             begin
                   counter256[8:0]=counter256[8:0]+9'b000000001;
             end
       end
   else
       begin
            counter664[9:0]=counter664[9:0]+10'b0000000001;
       end
end


always@(posedge clk or negedge resetn)
begin
   if(~resetn)
      begin
           red_duty_in[7:0]=8'b00000000;
           green_duty_in[7:0]=8'b00000000;
           blue_duty_in[7:0]=8'b00000000;
      end
    else if(chipselect&&write)
	      begin
	           red_duty_in[7:0]=wdata[23:16];
	           green_duty_in[7:0]=wdata[15:8];
	           blue_duty_in[7:0]=wdata[7:0];
	      end
	else
	    begin
	         red_duty_in[7:0]=red_duty_in[7:0];
	         green_duty_in[7:0]=green_duty_in[7:0];
	         blue_duty_in[7:0]=blue_duty_in[7:0];
	    end
     
end



always@(posedge clk or negedge resetn)
begin
     if(~resetn)
        begin
	        red_out=1'b0;
	        green_out=1'b0;
	        blue_out=1'b0;
        end
     else
        begin
          if(counter256[8:0]<=red_duty_out[7:0])
             begin
                  red_out=1'b1;
             end
          else
                  red_out=1'b0;

		  if(counter256[8:0]<=green_duty_out[7:0])
		     begin
		          green_out=1'b1;
		     end
		  else
		          green_out=1'b0;

		  if(counter256[8:0]<=blue_duty_out[7:0])
			 begin
				  blue_out=1'b1;
			 end
		  else
				  blue_out=1'b0;
        end   
end

endmodule